MSM7524 데이터 시트보기 (PDF) - Oki Electric Industry
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MSM7524 Datasheet PDF : 21 Pages
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¡ Semiconductor
MSM7524
Pin No.
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Name
AG
VDD
PON
X1
X2
CLKO
SCLK
CS
ADO
R/W
D4
D3
D2
D1
I/O
Description
Analog ground, 0 V.
—
This pin should be common with DG (pin 23) at the system ground point.
— Power supply, +5 V.
Power down control.
When digital "1" is applied to PON, the whole circuitry on chip falls
I
into the power down mode.
This pin is pulled-up to digit "1" internaly.
X1 and X2 are connected to a 3.579545 MHz crystal to generate a
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crystal clock for the chip.
If required to use an external clock, X1 should be left open and X2
O
should be connected to the external clock source via a capacitor
of 100 pF.
O 3.579545 MHz clock output.
External processor interface clock input.
During "WRITE" mode, the data on D4 to D1 pins are written into the
internal register at the falling edge of SCLK. During "READ" mode,
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the output data from the internal register appears on D4 to D1 pins
at the rising edge of SCLK.
SCLK is not required to be a periodic clock pulse stream. SCLK is
internally pulled-down to digital "0".
Chip select.
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When CS is on digital "0", "READ" and "WRITE" operations become
possible. CS is internally pulled-down.
Address data input.
When digital "1" is applied to AD0, data writing into the control
register and data reading out from the status register become possible.
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When digital "0" is applied to, data writing into the DTMF tone transmit
register and data reading out from the DTMF tone receive register
become possible. AD0 is internally pulled-down.
"READ" and "WRITE" control signal input.
"READ" or "WRITE" operation becomes possible during digital "1" or "0",
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respectively.
R/W is internally pulled-down to digital "0".
I/O
I/O 4-bit micro-processor interface bus.
I/O All pins are internally pulled-down.
I/O
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