MT8924 데이터 시트보기 (PDF) - Mitel Networks
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MT8924 Datasheet PDF : 14 Pages
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MT8924
Preliminary Information
AC Electrical Characteristics - Clocked Timing* (TOP=0 to 70°C; VDD=5V±5%)
Characteristics
Sym
Min Typ Max Units Test Conditions
1 Clock period
tCK
230
2 Clock low level width
tWLCK
100
3 Clock high level width
tWHCK
100
4 Clock rise time
tRCK
5 Clock fall time
tFCK
6 Sync. low setup time
tSLSY
50
7 Sync. low level hold time
tHLSY
40
8 Sync. high setup time
tSHSY
80
9 Sync. high width
tWHSY
tCK
10 OS propagation delay from rising
edge of Clock
tPDOS
ns
ns
ns
25
ns
25
ns
ns **
ns
ns
ns
100
ns CL=50pF
11 Cko propagation delay to Clock
edges
tPDEC
80
ns CL=50pF
12 TD setup time
tSTD
80
ns
13 TD hold time
tHTD
40
ns
14 TD setup time
tSTF
80
ns
15 TD hold time
tHTD
40
ns
* All AC characteristics are valid 250µs after VDD and the clock have been applied. CL is the max. capacitive load and RL is the test pull up
resistor. With Extra Bit Insert operating mode these times are 80ns longer.
** With Extra Bit Insert operating mode this time becomes 3tCK.
Cki
F0i
TD
TF
Cko
tCK
tRCK
tFCK
tWHCK
tWLCK
tSLSY
tHLSY
tSHSY
tSTD tHTD
tWHSY
tSTF tHTF
tPDEC tPDEC
tPDOS
OS
Figure 5 - Clock Timing
8-12
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