MX7839 데이터 시트보기 (PDF) - Maxim Integrated
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MX7839 Datasheet PDF : 14 Pages
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Octal, 13-Bit Voltage-Output DAC
with Parallel Interface
Pin Description
PIN
1
2
3
4
5, 38
6, 29
7
8
9
10
11
12
13
14
15–27
28
30
31
NAME
DUTGNDAB
OUTA
REFAB-
REFAB+
VDD
VSS
LDAC
A2
A1
A0
CS
WR
VCC
GND
DB0–DB12
CLR
REFGH+
REFGH-
FUNCTION
Device Sense Ground Input for OUTA and OUTB. In normal operation, OUTA and OUTB are referenced
to DUTGNDAB. When CLR is low, OUTA and OUTB are forced to the potential on DUTGNDAB.
DAC A Buffered Output Voltage
Negative Reference Input for DACs A and B
Positive Reference Input for DACs A and B
Positive Analog Power Supply. Normally set to +15V. Connect both pins to the supply voltage. See the
Power Supplies, Grounding, and Bypassing section for bypass requirements.
Negative Analog Power Supply. Normally set to -15V. See the Power Supplies, Grounding, and
Bypassing section for bypass requirements.
Load Input. Drive this asynchronous input low to transfer the contents of the input latches to their
respective DAC latches. DAC latches are transparent when LDAC is low and latched when LDAC is
high.
Address Bit 2 (MSB)
Address Bit 1
Address Bit 0 (LSB)
Chip Select. Active-low input.
Write Input. Active-low strobe for conventional memory write sequence. Input data latches are transpar-
ent when WR and CS are both low. WR latches data into the DAC input latch selected by A2, A1, A0 on
the rising edge of CS.
Digital Power Supply. Normally set to +5V. See the Power Supplies, Grounding, and Bypassing section
for bypass requirements.
Ground
Data Bits 0–12. Offset binary coding.
Clear Input. Drive CLR low to force all DAC outputs to the voltage on their respective DUTGND _ _.
Does not affect the status of internal registers. All DACs return to their previous levels when CLR goes
high.
Positive Reference Input for DACs G and H
Negative Reference Input for DACs G and H
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