MX7839 데이터 시트보기 (PDF) - Maxim Integrated

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MX7839

Octal, 13-Bit Voltage-Output DAC with Parallel Interface

Maxim Integrated 

Octal, 13-Bit Voltage-Output DAC

with Parallel Interface

CLR

R

R

2R

2R

2R

2R

D0

D12

D13

REF-

OUT

2R

2R

DUTGND

REF+

Figure 1. DAC Simplified Circuit

t1

CS

t4

t2

WR

t8

A0–A2

t5

t9

DB0–DB12

LDAC

t6

t7

t3

(NOTE 3)

t3

NOTES:

1. ALL INPUT RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF

+5V. tr = tf = 5ns.

2. MEASUREMENT REFERENCE LEVEL IS (VINH + VINL) / 2.

3. IF LDAC IS ACTIVATED WHILE WR IS LOW, THEN LDAC MUST STAY LOW

FOR t3 OR LONGER AFTER WR GOES HIGH.

Figure 2a. Digital Timing Diagram

_______________Detailed Description

Analog Section

The MX7839 contains eight 13-bit voltage-output DACs.

These DACs are inverted R-2R ladder networks that

convert 13-bit digital inputs into equivalent analog out-

put voltages, in proportion to the applied reference volt-

ages (Figure 1). The MX7839 has three positive

reference inputs (REF_ _ _ _+) and three negative refer-

ence inputs (REF_ _ _ _-). The difference from

REF_ _ _ _+ to REF_ _ _ _-, multiplied by two, sets the

DAC output span.

In addition to the differential reference inputs, the

MX7839 has four analog-ground input pins

(DUTGND_ _). When CLR is high (unasserted), the volt-

age on DUTGND_ _ offsets the DAC output voltage

range. If CLR is asserted, the output amplifier is forced

to the voltage present on DUTGND_ _.

Reference and DUTGND Inputs

All of the MX7839’s reference inputs are buffered with

precision amplifiers. This allows the flexibility of using

resistive dividers to set the reference voltages. Because

of the relatively high multiplying bandwidth of the refer-

ence input (188kHz), any signal present on the reference

pin within this bandwidth is replicated on the DAC output.

The DUTGND pins of the MX7839 are connected to the

negative source resistor (nominally 115kΩ) of the out-

put amplifier. The DUTGND pins are typically connect-

ed directly to analog ground. Each of these pins has an

input current that varies with the DAC digital code. If

the DUTGND pins are driven by external circuitry, bud-

get ±200µA per DAC for load current.

Output-Buffer Amplifiers

The MX7839’s voltage outputs are internally buffered by

precision gain-of-two amplifiers with a typical slew rate

of 1V/µs. With a full-scale transition at its output, the

typical settling time to ±1/2 LSB is 31µs. This settling

time does not significantly vary with capacitive loads

less than 10,000pF.

CLR

VOUT_

t10

t10

Figure 2b. Digital Timing Diagram

_______________________________________________________________________________________ 9

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