NXP Semiconductors
74F269
8-bit bidirectional binary counter
5. Pinning information
5.1 Pinning
74F269
U/D 1
Q0 2
Q1 3
Q2 4
Q3 5
Q4 6
GND 7
Q5 8
Q6 9
Q7 10
CP 11
CEP 12
24 PE
23 D0
22 D1
21 D2
20 D3
19 VCC
18 D4
17 D5
16 D6
15 D7
14 TC
13 CET
001aai981
Fig 5. Pin configuration SO24 and SSOP24 package
5.2 Pin description
Table 2. Pin description
Symbol Pin
U/D
1
Q0 to Q7 2, 3, 4, 5, 6, 8, 9, 10
GND
7
CP
11
CEP
12
CET
13
TC
14
D0 to D7 23, 22, 21, 20, 18, 17, 16, 15
VCC
19
PE
24
Description
up or down count control input
data output
ground (0 V)
clock input
count enable parallel input (active LOW)
count enable trickle input (active LOW)
terminal count output (active LOW)
data input
supply voltage
parallel enable input (active LOW)
Unit load
HIGH/LOW
1.0/1.0
50/33
-
1.0/1.0
1.0/1.0
1.0/1.0
50/33
1.0/1.0
-
1.0/1.0
[1] One FAST Unit Load (UL) is defined as 20 μA in HIGH state, 0.6 μA in LOW state.
Load value[1]
HIGH/LOW
20 μA/0.6 mA
1.0 mA/20 mA
-
20 μA/0.6 mA
20 μA/0.6 mA
20 μA/0.6 mA
1.0 mA/20 mA
20 μA/0.6 mA
-
20 μA/0.6 mA
74F269_5
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 25 March 2010
© NXP B.V. 2010. All rights reserved.
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