NCP1282D 데이터 시트보기 (PDF) - ON Semiconductor
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NCP1282D Datasheet PDF : 23 Pages
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NCP1282
The SYNC pin is in a high impedance mode during the
charging of the RTCT Ramp. In this period the oscillator
accepts an external SYNC pulse. If no pulse is detected
upon reaching the peak of the RTCT Ramp, a 100 ns SYNC
pulse is generated. The SYNC pulse is generated by
internally pulling the SYNC pin to VREF. The peak voltage
of the SYNC pin is typically 4.3 V. Once the 100 ns timer
expires, the pin goes back into a high impedance mode and
an external resistor is required for pulldown as shown in
Figure 49.
VREF
RT
RTCT
CT
SYNC
RSYNC
Figure 49. SYNC Pulse
The slew rate of the sync pin is determined by the pin
capacitance and external pulldown resistor. The maximum
source current of the SYNC pin is 1.0 mA. The resistor is
sized to allow the SYNC pin to discharge before the start
of the next cycle.
If an external pulse is received on the SYNC pin before
the internal pulse is generated, the controller enters the
slave mode of operation. Once operation in slave mode
commences, CT begins discharging and the RTCT Ramp
upper threshold is increased to 4.0 V.
If a controller in slave mode does not receive a sync pulse
before reaching the RTCT Ramp peak voltage (4.0 V), the
upper threshold is reset back to 3.0 V and the converter
reverts to operation in master mode. To guarantee the
converter stays in slave mode, the minimum clock period
of the master controller has to be less than the RTCT charge
time from 2.0 V to 4.0 V.
Two NCP1282’s are synchronized by connecting their
SYNC pins together. The first device that generates a sync
pulse during powerup becomes the master. A diode
connected as shown in Figure 50 can be used to
permanently set one controller as the master. The diode
prevents the master from receiving the SYNC pulse of the
slave controller.
MASTER
CONTROLLER
SYNC
RSYNC1
SYNC
RSYNC2
SLAVE
CONTROLLER
Figure 50. Master−Slave Configuration
5.0 V Reference
The NCP1282 has a precision 5.0 V reference output. It
is a buffered version of the internal reference. The 5.0 V
reference is biased directly from VAUX and it can supply up
to 5.0 mA. Load regulation is 50 mV and line regulation is
100 mV within the specified operating range.
It is required to bypass the reference with a capacitor.
The capacitor is used for compensation of the internal
regulator and high frequency noise filtering. The capacitor
should be placed across the VREF and GND pins. In most
applications a 0.1 mF will suffice. A bigger capacitor may
be required to reduce the voltage ripple caused by the
oscillator current. The recommended capacitor range is
between 0.047 mF and 1.0 mF.
During powerup, the 5.0 V reference is enabled once
VAUX reaches VAUX(on) and a UV fault is not present.
Otherwise, the reference is enabled once the UV fault is
removed and VAUX reaches VAUX(on).
Once a UV fault is detected after the reference has been
enabled, the reference is disabled after the soft−stop
sequence is complete if the UV fault is still present. If the
UV fault is removed before soft−stop is complete, the
reference is not disabled.
Application Information
ON Semiconductor provides an electronic design tool, a
demonstration board and an application note to facilitate
design of the NCP1282 and reduce development cycle
time. All the tools can be downloaded or ordered at
www.onsemi.com.
The electronic design tool allows the user to easily
determine most of the system parameters of an active
clamp forward converter. The tool evaluates the power and
active clamp stages as well as the frequency response of the
system. The tool allows the user to design a dual output
converter. The demo board delivers 240 W and has a 12 V
and a 5 V output. The circuit schematic is shown in
Figure 51. The converter design is described in
Application Note ANDxxxx.
http://onsemi.com
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