PI5A100
Precision, Wide-Bandwidth, Quad SPDT Analog Switch
Test Circuits/Timing Diagrams
Switch
Input +3V*
Logic
Input
NO
or NC
+5V
Vcc
COM
IN
GND
RL
100Ohm
VOUT
CL
15pF
Logic +3V
Input
0V
Switch
Output
0V
CL INCLUDES FIXTURE AND STRAY CAPACITANCE
( ) VOUT = VNO
RL
RL + RON
Figure 1. Switching Time
50%
tr <20ns
tf <20ns
VOUT
90%
tOFF
90%
tON
LOGIC INPUT WAVEFORMS INVERTED FOR
SWITCHES THAT HAVE OPPOSITE LOGIC
* 1.5V FOR 3.3V SUPPLY
VGEN
RGEN
COM
.1µF
+5V
V+
NO or
NC
Logic
Input
IN
GND
VOUT
CL
1nF
VOUT
IN OFF
IN OFF
Figure 2. Charge Injection
ON
ON
Q = (∆VOUT)(CL)
∆VOUT
OFF
OFF
7
PS7012H
08/30/04