HI2302JCQ(1997) 데이터 시트보기 (PDF) - Intersil

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HI2302JCQ
(Rev.:1997)

8-Bit, 50 MSPS, Video A/D Converter with Clamp Function

Intersil 

Timing Diagrams

CLOCK 1.3V

ANALOG INPUT

DATA OUTPUT

tPW1 tPW0

N

N-3

HI2302

N+1

N-2

N+2

N-1

N+3

N

N+4

N+1

= ANALOG SIGNAL SAMPLING POINT

FIGURE 1A. TIMING CHART

tr

tf

4ns

4ns

90%

3V

CLOCK

1.3V

10%

0V

0.7 DVDD

DATA OUTPUT

0.3 DVDD

tPLH,

tPHL

FIGURE 1B. TIMING CHART

tr = 4.5ns

OE INPUT

1.3V

tPLZ

tf = 4.5ns

90%

10%

tPZL

OUTPUT 1

OUTPUT 2

tPHZ

10%

90%

1.3V

tPZH

1.3V

FIGURE 1C. TIMING CHART

3V

0V

VOH

VOL (≠DVSS)

VOH (≠DVDD)

VOL

4-5

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