RT8223A 데이터 시트보기 (PDF) - Richtek Technology

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RT8223A

High Efficiency, Main Power Supply Controller for Notebook Computers

Richtek Technology 

RT8223A/B

maximum duty factor, which can be calculated from the Output Capacitor Stability

on-time and minimum off-time :

Stability is determined by the value of the ESR zero relative

VSAG

=

(ΔILOAD )2 × L × ⎛⎜⎝K

VOUTx

VIN

+ TOFF(MIN) ⎞⎟⎠

2 × COUT

×

VOUTx

×

⎢⎣⎡K ⎛⎜⎝

VIN

− VOUTx

VIN

⎞⎟⎠

−

TOFF(MIN)

⎤

⎥⎦

to the switching frequency. The point of instability is given

by the following equation :

fESR

=

1

2 × π × ESR × COUT

≤

fSW

4

Where minimum off-time (TOFF(MIN)) = 300ns (typ.) and K

is from Table 1.

Output Capacitor Selection

The output filter capacitor must have low enough ESR to

meet output ripple and load-transient requirements, yet

have high enough ESR to satisfy stability requirements.

Also, the capacitance value must be high enough to

absorb the inductor energy going from a full load to no

load condition without tripping the OVP circuit.

For CPU core voltage converters and other applications

where the output is subject to violent load transients, the

output capacitor's size depends on how much ESR is

needed to prevent the output from dipping too low under a

load transient. Ignoring the sag due to finite capacitance :

ESR ≤

VP-P

ILOAD(MAX)

In non-CPU applications, the output capacitor's size

depends on how much ESR is needed to maintain an

acceptable level of output voltage ripple :

ESR ≤

VP-P

LIR × ILOAD(MAX)

where VP-P is the peak to peak output voltage ripple.

Do not put high-value ceramic capacitors directly across

the outputs without taking precautions to ensure stability.

Large ceramic capacitors can have a high- ESR zero

frequency and cause erratic, unstable operation. However,

it is easy to add enough series resistance by placing the

capacitors a couple of inches downstream from the

inductor and connecting VOUTx or the FBx divider close

to the inductor.

Unstable operation manifests itself in two related and

distinctly different ways: double pulsing and feedback loop

instability.

Double pulsing occurs due to noise on the output or

because the ESR is so low that there is not enough voltage

ramp in the output voltage signal. This “fools” the error

comparator into triggering a new cycle immediately after

the 300ns minimum off-time period has expired. Double

pulsing is more annoying than harmful, resulting in nothing

worse than increased output ripple. However, it may

indicate the possible presence of loop instability, which

is caused by insufficient ESR.

Loop instability can result in oscillations at the output

after line or load perturbations that can trip the overvoltage

protection latch or cause the output voltage to fall below

the tolerance limit.

Organic semiconductor capacitor(s) or specialty polymer

capacitor(s) are recommended.

For low input to output voltage differentials (VIN / VOUTx

< 2), additional output capacitance is required to maintain

stability and good efficiency in ultrasonic mode.

The amount of overshoot due to stored inductor energy

can be calculated as :

VSOAR ≤

(IPEAK )2 × L

2 × COUT × VOUTx

where IPEAK is the peak inductor current.

The easiest method for checking stability is to apply a

very fast zero to max load transient and carefully observe

the output voltage ripple envelope for overshoot and ringing.

It helps to simultaneously monitor the inductor current

with an AC current probe. Do not allow more than one

cycle of ringing after the initial step response under or

overshoot.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum operation junction temperature. The maximum

power dissipation depends on the thermal resistance of

IC package, PCB layout, the rate of surroundings airflow

DS8223A/B-04 April 2011

www.richtek.com

23

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