RT8204A 데이터 시트보기 (PDF) - Richtek Technology

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RT8204A

Single Synchronous Buck with LDO Controller

Richtek Technology 

RT8204A

LDO_VIN

LDRV

LFB

LDO_VOUT

R3

R4

Figure 8. LDO Output Voltage Setting

LDO Output Capacitor Selection

Low ESR capacitors such as Sanyo POSCAPs or

Panasonic SP-caps are recommended for bulk

capacitance, and ceramic bypass capacitors are

recommended for decoupling high frequency transients.

LDO Input Capacitor Selection

Low ESR capacitors such as Sanyo POSCAPs or

Panasonic SP-caps are recommended for the input

capacitors to provide better load transient response. If the

LDO input is connected from the output of buck converter

(VOUT1), a 0.1μF ceramic capacitor will sufficient.

LDO MOSFET Selection

Low threshold N-MOSFETs are required. For the device

to work under all operating conditions, a maximum RDS(ON)

must be met to ensure that the output will not go into

dropout :

RDS(ON)(MAX)

=

VIN(MIN) − VOUT(MAX)

IOUT(PEAK)

Ω

Note that RDS(ON) must be met for operating temperature

range at the minimum VGS condition.

Power consumptions of the N-MOSFETs should be taken

into consideration for the selection of various package

types.

Layout Considerations

Layout is very important in high frequency switching

converter design. If the Layout is designed improperly,

the PCB could radiate excessive noise and contribute to

the converter instability. Certain points must be considered

before starting a layout for the RT8204A.

` Connect an RC low pass filter from VDDP to VDD, 1μF

and 10Ω are recommended. Place the filter capacitor

close to the IC.

` Keep current limit setting network as close as possible

to the IC. Routing of the network should avoid coupling

to high voltage switching node.

` Connections from the drivers to the respective gate of

the high side or the low side MOSFET should be as

short as possible to reduce stray inductance.

` All sensitive analog traces and components such as

VOUT, FB, GND, EN/DEM, PGOOD, OC, VDD, and

TON should be placed away from high voltage switching

nodes such as PHASE, LGATE, UGATE, or BOOT

nodes to avoid coupling. Use internal layers as ground

planes and shield the feedback trace from power traces

and components.

` Current sense connections must always be made using

Kelvin connections to ensure an accurate signal, with

the current limit resistor located at the device.

` Power sections should connect directly to ground planes

using multiple vias as required for current handling

(including the chip power ground connections). Power

components should be placed to minimize loops and

reduce losses.

www.richtek.com

18

DS8204A-05 April 2011

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