RT9719AGQW 데이터 시트보기 (PDF) - Richtek Technology
부품명
상세내역
제조사
RT9719AGQW Datasheet PDF : 10 Pages
| |||
RT9719
junction to ambient. The maximum power dissipation can
be calculated by following formula :
PD(MAX) = ( TJ(MAX) − TA ) / θJA
Where TJ(MAX) is the maximum operation junction
temperature, TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT9719, where TJ(MAX) is 125°C and TA is the operated
ambient temperature. The junction to ambient thermal
resistance θJA for WDFN-8L 2x2 package is 165°C/W and
SOT-23-6 package is 250°C/W on the standard JEDEC
51-3 single-layer thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by following
formula :
PD(MAX) = (125°C − 25°C) / (165°C/W) = 0.606 W for
WDFN-8L 2x2 packages
PD(MAX) = (125°C − 25°C) / (250°C/W) = 0.400 W for
SOT-23-6 packages
The maximum power dissipation depends on operating
ambient temperature for fixed TJ(MAX) and thermal
resistance θJA . For RT9719 packages, the Figure 3 of
derating curves allows the designer to see the effect of
rising ambient temperature on the maximum power
allowed.
1.0
0.9
WDFN-8L 2x2
0.8
Four Layouts PCB
0.7
0.6 SOT-23-6
0.5
0.4
0.3
0.2
0.1
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Layout Consideration
The RT9719 is a protection device. Careful PCB layout is
necessary. For best performance, place all peripheral
components as close to the IC as possible. A short
connection is highly recommended. The following
guidelines should be strictly followed when designing a
PCB layout for the RT9719.
` The exposed pad, GND must be soldered to a large
ground plane for heat sinking and noise prevention. The
through-hole vias located at the exposed pad is
connected to ground plane of internal layer.
` ACIN traces should be wide to minimize inductance and
handle the high currents. The trace running from input
to chip should be placed carefully and shielded strictly.
` The capacitors must be placed close to the part. The
connection between pins and capacitor pads should be
copper traces without any through-hole via connection.
From Adapter ACIN 1
ACIN 2
ACIN 3
CIN GND 4
8 ISENSE
7 ISENSE
To Battery
6 CHRIN
9 5 GATEDRV
To Baseband
Gate Controller
To Baseband
Charger Controller
GND
Input capacitor must be
placed between GND
and ACIN to reduce
noise.
The exposed pad,
GND must be soldered
to a large ground plane
for heat sinking and
noise prevention.
The capacitor must be
placed between GND
and ACIN to reduce
noise.
NC
GND 2
From Adapter
ACIN 3
CIN
To Baseband
Gate Controller
6 GATEDRV
The capacitor
must be placed
between GND
and ACIN to
reduce noise.
5 CHRIN To Baseband Charger Controller
4 ISENSE
To Battery
GND
Input capacitor must be
placed between GND
and ACIN to reduce
noise.
The exposed pad,
GND must be soldered
to a large ground
plane for heat sinking
and noise prevention.
Figure 4. PCB Layout Guide
Figure 3. Derating Curves for RT9719 Packages
www.richtek.com
8
DS9719-01 April 2011
Share Link: 