S1M8821/22/23
PIN CONFIGURATION
INTERGER RF/IF DUAL PLL
VDD1 1
Vp1 2
CPoRF 3
GND 4
(Digital)
finRF 5
finRF 6
GND 7
(Analog)
OSCin 8
GND 9
(Digital)
foLD 10
S1M8821
S1M8822
S1M8823
20 VDD2
19 Vp2
18 CPoIF
17 GND
(Digital)
16 finIF
15 finIF
14 GND
(Analog)
13 LE
12 DATA
11 CLOCK
20-TSSOP
20-Lead(0.173 Wide) Thin Shrink Small
Outline Package(20-TSSOP)
NOTES:
1. pin #9 = pin #17(internally connected).
2. Do not tie up Vp and VDD
: Vp is the source of digital noises. The power for analog part is supplied by VDD.
If Vp and VDD are tied together, noisy Vp corrupts the power source for the analog part.
4