S34ML01G104BFI003 데이터 시트보기 (PDF) - Spansion Inc.
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S34ML01G104BFI003 Datasheet PDF : 73 Pages
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Data Sheet (Preliminary)
1.6 Addressing
1.6.1
S34ML01G1
Table 1.3 Address Cycle Map — 1 Gb Device
Bus Cycle
I/O [15:8] (3)
I/O0
I/O1
I/O2
I/O3
x8
1st
—
A0
A1
A2
A3
2nd
—
A8
A9
A10
A11
3rd
—
A12
A13
A14
A15
4th
—
A20
A21
A22
A23
x16
1st
Low
A0
A1
A2
A3
2nd
Low
A8
A9
A10
L (2)
3rd
Low
A11
A12
A13
A14
4th
Low
A19
A20
A21
A22
Notes:
1. L must be set to low.
2. Block address concatenated with page address = actual page address.
3. I/O[15:8] are not used during the addressing sequence and should be driven Low.
I/O4
A4
L (1)
A16
A24
A4
L (2)
A15
A23
I/O5
A5
L (1)
A17
A25
A5
L (2)
A16
A24
I/O6
A6
L (1)
A18
A26
A6
L (2)
A17
A25
I/O7
A7
L (1)
A19
A27
A7
L (2)
A18
A26
For the address bits, the following rules apply:
A0 - A11: column address in the page
A12 - A17: page address in the block
A18 - A27: block address
September 6, 2012 S34ML01G1_04G1_10
Spansion® SLC NAND Flash Memory for Embedded
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