S6B0796 데이터 시트보기 (PDF) - Samsung

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S6B0796

240 SEG / COM DRIVER FOR STN LCD

Samsung 

S6B0796 PRELIMINARY SPEC. VER. 1.0

240 SEG / COM DRIVER FOR STN LCD

Common Mode

Symbol

VDD

VSS

V0R, V0L

V12R , V12L

V43R , V43L

V5R , V5L

EIO1

EIO2

LP

L/R

Function

Logic system power supply pin connects to +2.4 to +5.5V

Ground pin connects to 0 V

Power supply pin for LC driver voltage bias.

. Normally, the bias voltage used is set by a resistor divider.

. Ensure that voltage are set such that VSS<V43<V12<V0.

. To further reduce the difference between the output waveforms of LC driver

output pins Y1 and Y240, externally connect ViR and ViL(i=0, 12, 43, 5)

Bidirectional shift register shift data input/output pin

. Output pin when L/R is at VSS level “L”, input pin when L/R is at VDD level

“H”.

. When EIO1 is used as input pin, it will be pull-down.

. When EIO1 is used as output pin, it won’t be pull-down.

Bidirectional shift register shift data input/output pin

. Input pin when L/R is at VSS level “L”, output pin when L/R is at VDD level

“H”.

. When EIO2 is used as input pin, it will be pull-down.

. When EIO2 is used as output pin, it won’t be pull-down.

Bidirectional shift register shift clock pulse input pin

. Data is shifted on the falling edge of the clock pulse.

Bidirectional shift register shift direction selection pin

. Data is shifted from Y240 to Y1 when set to VSS to level “L”, and data is

shifted from Y1 to Y240 when set to VDD level “H”.

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