55 COM / 100 SEG DRIVER & CONTROLLER FOR STN LCD
S6B0717
MICROPROCESSOR INTERFACE
Table 7. Microprocessor Interface Pins Description
Name
I/O
Description
RESETB
I
Reset input pin
When RESETB is “L”, initialization is executed.
Parallel / Serial data input select input
PS
C68
CS1B
CS2
RS
RW_WR
PS
Interface
mode
Chip
Data /
select instruction
Data
Read / Write Serial clock
I
H
Parallel
CS1B,
CS2
RS
DB0 to DB7
E_RD
RW_WR
-
L
Serial
CS1B,
CS2
RS
SID (DB7) Write only SCLK (DB6)
*NOTE: In serial mode, it is impossible to read data from the on-chip RAM. And DB0 to
DB5 are high impedance and E_RD and RW_WR must be fixed to either “H” or “L”.
Microprocessor interface select input pin
I
− C68 = "H": 6800-series MPU interface
− C68 = "L": 8080-series MPU interface
Chip select input pins
I Data / instruction I/O is enabled only when CS1B is “L” and CS2 is “H”. When chip
select is non-active, DB0 to DB7 may be high impedance.
Register select input pin
I
− RS = "H": DB0 to DB7 are display data
− RS = "L": DB0 to DB7 are control data
Read / Write execution control pin
C68 MPU type RW_WR
Description
Read/Write control input pin
H 6800-series
RW
− RW = “H”: read
I
− RW = “L”: write
L 8080-series
/WR
Write enable clock input pin
The data on DB0 to DB7 are latched at the rising
edge of the /WR signal.
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