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SAA2502H

ISO/MPEG Audio Source Decoder

Philips Electronics 

Philips Semiconductors

ISO/MPEG Audio Source Decoder

Preliminary specification

SAA2502

handbook, full pagewidth

220 pF

neg 10 kΩ

SAA2502H pos

10 kΩ

10 kΩ

390 pF

10 kΩ

220 pF

11 kΩ

100 µF

output

TDA1308T

11 kΩ

+2.5 V

10 kΩ

MBH974

Fig.17 External low-pass filters

7.6 Control interface module

7.6.1 RESETTING

Table 18 Resetting is performed by 2 signals

SIGNAL

STOP

RESET

DIRECTION

FUNCTION

input soft reset and stop decoding

input

hard reset: force default

settings

A rising edge of the signal STOP triggers the next event.

The decoding process is interrupted and the input buffer is

flushed. Consequently audio frame synchronization is

abandoned and the decoder starts searching for a new

sync in the coded input data stream. In the meantime the

output interface is soft muted (i.e. the output signal fades

away in approximately 500 samples).

There are several other events that have the same effect

as a rising edge of the STOP signal:

• Change of the current MPEG layer in the input stream

• Change of the current sampling frequency in the input

stream

• Change of the current bit rate in the input stream

(variable bit rate is NOT supported)

• Change of current input interface mode

(INMOD1 and 0) and/or audio frame synchronization

mode (SYMOD1 and 0) setting

• Enforcement of a soft reset through the control interface.

There is also a level triggered effect which remains

provided STOP is asserted. When the STOPRQ control

flag is set input data requesting will be halted, otherwise

normal input interface behaviour will continue at the bit rate

that was valid before STOP assertion but all data is

considered to be unreliable (as if CDEF were asserted).

Consequently frame synchronization and decoding will not

resume until STOP is de-asserted.

The hard reset signal RESET has the same effect as

STOP but it will also force the control interface settings into

their default states. RESET must stay high during at least

24 MCLKIN periods if MCLK24 = logic 1 or 12 MCLKIN

periods if MCLK24 = logic 0.

7.6.2 INTERRUPTS

The SAA2502 is able to generate an interrupt upon the

occurrence of one or more of the following events:

• Status bit DST0 has been set (i.e. ancillary/PAD data,

frame headers and error report are available)

• Rising edge of STOP input signal

• MPEG CRC check failed

• Status bit INSYNC has been set

• Status bit INSYNC has been cleared.

For more information on these items see Sections 7.6.6.1

and 7.6.6.9.

Each of these interrupts sources may be enabled or

disabled as required by the application. After a hard reset

all interrupt sources are disabled. When the host

processor is interrupted by the SAA2502 it should read the

interrupt event register to find out which event or events

caused the interrupt. Reading this register will also clear all

pending interrupts.

The interrupt pin is active LOW (INT = logic 0 indicates an

interrupt) and it is of the ‘open drain’ type. Consequently it

is allowed to ‘wire OR’ this pin with interrupt pins of the

same type of other devices. For correct operation an

external pull-up resistor should be provided.

1997 Nov 17

27

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