ST7538 데이터 시트보기 (PDF) - STMicroelectronics

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ST7538

FSK POWER LINE TRANSCEIVER

STMicroelectronics 

ST7538

Table 5. Electrical Characteristcs (continued)

(AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C ≤ Tamb ≤ 85°C, Fc = 86kHz, other Control

Register parameters as default value, unless otherwise specified).

Symbol

RIN

VCD

Parameter

Input Impedance

Carrier Detection Sensitivity

(Normal Mode)

Test Condition

Min.

80

Typ.

100

0.5

Max.

140

2

Unit

kΩ

mVrms

Carrier Detection Sensitivity

(High Sensitivity Mode)

250

µVrms

VBU

Band in Use Detection Level

77

85

dB/

µVrms

Voltage Regulator

VDC

Linear Regulator Output

Voltage

-25<Tj<125 C

0<I(VDC)<100mA

4.9 5.05 5.2

V

-25<Tj<125 C

4.7

5.2

V

0<I(VDC)<150mA

) ∆VDC Line Regulation

7.5V<PAVcc<12.5V

I(VDC)=10mA

10

50

mV

ct(s Load Regulation

5mA<I(VDC)<100mA

PAVcc=7.5V

20

75

mV

du I(VDC)

Linear Regulator Current

Limitation

150 180 210 mA

ro UVLO Input Under Voltage Lock Out

P Threshold

3.7

3.9

4.1

V

te UVLOHYS UVLO Hysteresis

340

mV

le PG

Power Good Output Voltage

o Threshold on VDC pin

4.3

4.5

4.7

V

s PGHYS PG Hysteresis

250

mV

b Other Functions

- O TRSTO Reset Time

See Figure 22; Xtal=16MHz

50

ms

) TWD Watch-dog Pulse Width

See Figure 22

3.5

ms

ct(s TWM Watch-dog Pulse Period

TWD +

3.5

1490 ms

u TWO Watch-dog Time Out

1.5

s

rod TOUT TX TIME OUT

Control Register Bit 7 and Bit 8

1

s

See Figure 21

3

P TOFF

Time Out OFF Time

See Figure 21

125

ms

te TOFFD RxTx 0->1 vs. TOUT Delay

20

µs

le TCD

Carrier Detection Time

Obso selectable by register

Control Register

bit 9 and bit10

Figure 12

500

µs

1

ms

3

ms

5

ms

TDCD CD_PD Propagation Delay

Figure 12

300 500

µs

MCLK

Master Clock Output

Selectable by register

Control Register

bit 15 and bit 16

see table 11

fclock

fclock/2

fclock/4

MHz

BAUD Baud rate

Control Register

bit 3 and bit 4

see table 11

600

1200

2400

4800

Baud

7/30

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