ST8016S 데이터 시트보기 (PDF) - Sitronix Technology Co., Ltd.
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ST8016S Datasheet PDF : 26 Pages
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ST8016S
10.2 AC Characteristics
(Segment Mode 1) (LGND =VSS = 0 V, VDD = +2.5 to +3.0 V, V0 = + 15.0 to +30.0 V, TOPR = -25 10+85 °C)
PARAMETER
SYMBOL CONDITIONS MIN TYP. MAX. UNIT NOTE
Shift clock period
tWCK
tR,tF ≤ 11ns
125
ns
1
Shift clock "H" pulse width
tWCKH
51
ns
Shift clock "L" pulse width
tWCKL
51
ns
Data setup time
tDS
30
ns
Data hold time
tDH
40
ns
Latch pulse "H" pulse width
tWLPH
51
ns
Shift clock rise to latch pulse rise
tLD
time
0
ns
Shift clock fall to latch pulse fall
tSL
time
51
ns
Latch pulse rise to shift clock rise
tLS
time
51
ns
Latch pulse fall to shift clock fall
tLH
time
51
ns
Enable setup time
tS
36
ns
Input signal rise time
tR
50
ns
2
Input signal fall time
tF
50
ns
2
DISPOFF removal time
tSD
100
ns
DISPOFF "L" pulse width
tWDL
1.2
µs
Output delay time (1)
tD
CL = 15 pF
78
ns
Output delay time (2)
tPD1, t PD2
CL = 15 pF
1.2 µs
Output delay time (3)
t PD3
CL = 15 pF
1.2 µs
NOTES:
1. Takes the cascade connection into consideration.
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
(Segment Mode 2)
(LGND =VSS = 0 V, VDD = +5.0±0.5 V, V0 = + 15.0 to +30.0 V, TOPR = -25 to +85 °C)
PARAMETER
SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Shift clock period
tWCK
tR,tF ≤ 10ns
66
ns
1
Shift clock "H" pulse width
tWCKH
23
ns
Shift clock "L” pulse width
tWCKL
23
ns
Data setup time
tDS
15
ns
Data hold time
tDH
23
ns
Latch pulse "H" pulse width
tWLPH
30
ns
Shift clock rise to latch pulse rise
tLD
0
ns
time
Shift clock fall to latch pulse fall
tSL
50
ns
time
Latch pulse rise to shift clock rise
tLS
30
ns
time
Latch pulse fall to shift clock fall
tLH
30
ns
time
Enable setup time
tS
15
ns
Input signal rise time
tR
50
ns
2
Input signal fall time
tF
50
ns
2
DISPOFF removal time
tSD
100
ns
DISPOFF "L" pulse width
tWDL
1.2
µs
Output delay time (1)
tD
CL = 15 pF
41
ns
Output delay time (2)
tPD1, t PD2
CL = 15 pF
1.2 µs
Output delay time (3)
t PD3
CL = 15 pF
1.2 µs
NOTES:
1. Takes the cascade connection into consideration.
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
Preliminary Ver 0.24
Page 17/26
2009/10/01
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