TC72
SPI READ DATA TRANSFER
(CP = 0, data shifted on rising edge of SCK, data clocked on falling edge of SCK, A7 = 0)
CE
tCC
SCK
tDC tCDH
SDI
A7 MSb
SDO
HIGH Z
1/fCLK
tF
tR
tCH tCL
A0 LSb
tCDD
D7 MSb
tCWH
tCCH
tCDZ
D0 LSb
HIGH Z
SPI WRITE DATA TRANSFER
(CP = 0, data shifted on rising edge of SCK, data clocked on falling edge of SCK, A7 = 1)
CE
tCWH
SCK
SDI
1/fCLK
tCC
tCCH
tF
tR
tCH tCL
tDC
tCDH
A7 = 1 MSb
A0 LSb D7 MSb
D0
LSb
Note: The timing diagram is drawn with CP = 0. The TC72 also functions with CP = 1;
however, the edges of SCK are reversed as defined in Table 3-3 and Figure 3-2.
FIGURE 1-1:
Serial Port Timing Diagrams.
2002 Microchip Technology Inc.
DS21743A-page 5