AD7868BNZ 데이터 시트보기 (PDF) - Analog Devices
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AD7868BNZ Datasheet PDF : 16 Pages
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AD7868–SPECIFICATIONS
ADC SECTION (VDD = +5 V ؎ 5%, VSS = –5 V ؎ 5%, AGND = DGND = 0 V, fCLK = 2.0 MHz external. All specifications TMIN to TMAX-
unless otherwise noted.)
Parameter
A
B
T
Version1 Version1 Version1 Units
Test Conditions/Comments
DYNAMIC PERFORMANCE2
Signal-to-Noise Ratio3, 4 (SNR) @ +25°C
70
72
70
dB min
VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz
TMIN to TMAX
70
71
70
dB min
Typically 71.5 dB for 0 < VIN < 41.5 kHz
Total Harmonic Distortion (THD)
–78
–78
–76
dB max
VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz
Typically 71.5 dB for 0 < VIN < 41.5 kHz
Peak Harmonic or Spurious Noise
–78
–78
–76
dB max
VIN = 10 kHz Sine Wave, fSAMPLE = 83 kHz
Typically 71.5 dB for 0 < VIN < 41.5 kHz
Intermodulation Distortion (IMD)
Second Order Terms
Third Order Terms
Track/Hold Acquisition Time
–78
–78
–76
dB max
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
–80
–80
–78
dB max
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE = 50 kHz
2
2
2
µs max
DC ACCURACY
Resolution
Minimum Resolution
Integral Nonlinearity
Integral Nonlinearity
Differential Nonlinearity
Bipolar Zero Error
Positive Gain Error5
Negative Gain Error5
12
12
12
Bits
12
12
12
Bits
No Missing Codes Are Guaranteed
± 12
± 12
± 12
LSB typ
±1
±1
LSB max
± 0.9
± 0.9
± 0.9
LSB max
±5
±5
±5
LSB max
±5
±5
±5
LSB max
±5
±5
±5
LSB max
ANALOG INPUT
Input Voltage Range
Input Current
REFERENCE OUTPUT6
RO ADC @ +25°C
RO ADC TC
RO ADC TC
Reference Load Sensitivity (∆RO ADC vs. ∆I)
±3
±3
±3
Volts
±1
±1
±1
mA max
2.99/3.01
± 25
–1.5
2.99/3.01
± 25
± 40
–1.5
2.99/3.01
± 25
± 50
–1.5
V min/V max
ppm/°C typ
ppm/°C max
mV max
Reference Load Current Change (0 µA–500 µA),
Reference Load Should Not Be Changed
During Conversion
LOGIC INPUTS (CONVST, CLK, CONTROL)
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Current7 (CONTROL Input Only)
Input Capacitance, CIN8
2.4
2.4
2.4
V min
VDD = 5 V ± 5%
0.8
0.8
0.8
V max
VDD = 5 V ± 5%
± 10
± 10
± 10
µA max
VIN = 0 V to VDD
± 10
± 10
± 10
µA max
VIN = VSS to DGND
10
10
10
pF max
LOGIC OUTPUTS
DR, RFS Outputs
Output Low Voltage, VOL
RCLK Output
Output Low Voltage, VOL
DR, RFS, RCLK Outputs
Floating-State Leakage Current
Floating-State Output Capacitance8
0.4
0.4
0.4
V max
ISINK = 1.6 mA, Pull-Up Resistor = 4.7 kΩ
0.4
0.4
0.4
V max
ISINK = 2.6 mA, Pull-Up Resistor = 2 kΩ
± 10
± 10
± 10
µA max
15
15
15
pF max
CONVERSION TIME
External Clock
Internal Clock
10
10
10
µs max
10
10
10
µs max
The Internal Clock Has a Nominal Value of 2.0 MHz
POWER REQUIREMENTS
VDD
VSS
IDD
ISS
Total Power Dissipation
For Both DAC and ADC
+5
+5
+5
V nom
± 5% for Specified Performance
–5
–5
–5
V nom
± 5% for Specified Performance
22
22
25
mA max
Cumulative Current from the Two VDD Pins
12
12
13
mA max
Cumulative Current from the Two VSS Pins
170
170
190
mW max Typically 130 mW
NOTES
1Temperature ranges are as follows: A/B Versions, –40°C to +85°C; T Version, –55°C to +125°C.
2VIN = ± 3 V
3SNR calculation includes distortion and noise components.
4SNR degradation due to asynchronous DAC updating during conversion is 0.1 dB typ.
5Measured with respect to internal reference.
6For capacitive loads greater than 50 pF a series resistor is required (see INTERNAL REFERENCE section).
7Tying the CONTROL input to VDD places the device in a factory test mode where normal operation is not exhibited.
8Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
–2–
REV. B
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