Table 10. SFR Descriptions
0/8
1/9
F8h
CH
0000 0000
F0h
B(1)
0000 0000
E8h
CL
0000 0000
E0h
ACC(1)
0000 0000
D8h
CCON
CMOD
00X0 0000 00XX X000
D0h
PSW(1)
0000 0000
PSW1(1)
0000 0000
C8h
T2CON
T2MOD
0000 0000 XXXX XX00
2/A
CCAP0H
0000 0000
CCAP0L
0000 0000
CCAPM0
X000 0000
RCAP2L
0000 0000
C0h
B8h
IPL0
X000 0000
SADEN
0000 0000
B0h
P3
1111 1111
IE1
IPL1
XX0X XXX0 XX0X XXX0
A8h
IE0
0000 0000
SADDR
0000 0000
A0h
P2
1111 1111
98h
SCON
SBUF
BRL
0000 0000 XXXX XXXX 0000 0000
90h
P1
1111 1111
SSBR
0000 0000
88h
TCON
0000 0000
TMOD
0000 0000
TL0
0000 0000
80h
P0
1111 1111
SP(1)
0000 0111
DPL(1)
0000 0000
0/8
1/9
2/A
3/B
CCAP1H
0000 0000
CCAP1L
0000 0000
CCAPM1
X000 0000
RCAP2H
0000 0000
IPH1
XX0X XXX0
BDRCON
XXX0 0000
SSCON(2)
TL1
0000 0000
DPH(1)
0000 0000
3/B
4/C
5/D
6/E
7/F
CCAP2H
0000 0000
CCAP3H
0000 0000
CCAP4H
0000 0000
FFh
F7h
CCAP2L
0000 0000
CCAP3L
0000 0000
CCAP4L
0000 0000
EFh
E7h
CCAPM2
X000 0000
CCAPM3
X000 0000
CCAPM4
X000 0000
DFh
D7h
TL2
0000 0000
TH2
0000 0000
CFh
C7h
SPH(1)
0000 0000
BFh
IPH0
X000 0000
B7h
AFh
WDTRST
1111 1111
WCON
XXXX XX00
A7h
P1LS
0000 0000
P1IE
0000 0000
P1F
0000 0000
9Fh
SSCS(3)
SSDAT
0000 0000
SSADR
0000 0000
97h
TH0
0000 0000
TH1
0000 0000
CKRL
POWM
0000 1000 0XXX XXXX
8Fh
DPXL(1)
0000 0001
PCON
0000 0000
87h
4/C
5/D
6/E
7/F
Reserved
Notes:
1. These registers are described in the TSC80251 Programmer’s Guide (C251 core registers).
2. In TWI and SPI modes, SSCON is splitted in two separate registers. SSCON reset value is 0000 0000 in TWI mode and
0000 0100 in SPI mode.
3. In read and write modes, SSCS is splitted in two separate registers. SSCS reset value is 1111 1000 in read mode and 0000
0000 in write mode.
16 AT/TSC8x251G2D
4135F–8051–11/06