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UPD16835AGS-BGG 데이터 시트보기 (PDF) - NEC => Renesas Technology
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UPD16835AGS-BGG
MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT
NEC => Renesas Technology
UPD16835AGS-BGG Datasheet PDF : 32 Pages
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µ
PD16835A
<7th byte>
Bit
Data
Function
Setting
D7
D6
4-bit data
β
ch
D5 input
Current Set2
D4
β
ch Output
current setting 2
EVR: 100 to 250 mV
Setting (0 to 15)
Note
D3
D2
4-bit data
β
ch
D1
input
Current Set1
D0
β
ch Output
current setting 1
EVR: 100 to 250 mV
Setting (0 to 15)
Note
Note
A voltage of about double EVR is output to
the FIL pin.
<8th byte>
Bit
Data
Function
Setting
D7 1 or 0
D6 1 or 0
D5 1 or 0
D4 1 or 0
D3 1 or 0
Checksum
Checksum
Note
D2 1 or 0
D1 1 or 0
D0 1 or 0
Note
Data is input so that the sum of the 1st
through the 8th bytes is 00H.
<7th byte>
Bit
Data
D7
1 or 0
D6
15-bit data
D5
D4
High-order
D3
7-bit data
D2
input
D1
D0
Function
Current Set
β
β
Pulse Width
Setting
set2/set1
β
ch pulse
cycle:
0.25 to 8191.75
µ
s
Setting
(1 to 32767)
∆
t = 0.25
µ
s
<8th byte>
Bit
Data
Function
Setting
D7
1 or 0
D6
1 or 0
D5
1 or 0
D4
1 or 0
D3
1 or 0
Checksum
Checksum
Note
D2
1 or 0
D1
1 or 0
D0
1 or 0
Note
Data is input so that the sum of the 1st
through the 8th bytes is 00H.
Data Sheet S15973EJ1V0DS
11
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