W986416DH-6I 데이터 시트보기 (PDF) - Winbond

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W986416DH-6I

1M x 4 BANKS x 16 BITS SDRAM

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W986416DH

Operating Timing Example, continued

Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge)

CLK

CS

(CLK = 100 MHz)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

tRC

RAS

CAS

WE

BS0

BS1

tRCD

A10 RAa

tRAS

tRP

tRAS

RBb

tRCD

tRCD

RAc

A0-A9 RAa

CAx

DQM

RBb

CBy

RAc

CAz

CKE

DQ

Bank #0 Active

Bank #1

Bank #2

Idle

Bank #3

tCAC

tCAC

ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1

tRRD

Read

Active

tRRD

AP*

Read

Active

* AP is the internal precharge start timing

tCAC

by4 by5 by6

CZ0

Read

AP*

- 27 -

Publication Release Date: April 11, 2002

Revision A4

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