WM8978GEFL/RV 데이터 시트보기 (PDF) - Wolfson Microelectronics plc

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WM8978GEFL/RV

Stereo CODEC With Speaker Driver

Wolfson Microelectronics plc 

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SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

MCLK

tMCLKL

tMCLKH

tMCLKY

WM8978

Figure 1 System Clock Timing Requirements

Test Conditions

DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK =

256fs, 24-bit data, unless otherwise stated.

PARAMETER

System Clock Timing Information

MCLK System clock cycle time

MCLK duty cycle

SYMBOL

TMCLKY

TMCLKDS

MIN

Tbd

60:40

TYP

MAX

UNIT

ns

40:60

AUDIO INTERFACE TIMING – MASTER MODE

Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)

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PP Rev 1.7 January 2005

11

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