HDM8513AP 데이터 시트보기 (PDF) - Hyundai Micro Electronics

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HDM8513AP

DVB/DSS Compliant Receiver

Hyundai Micro Electronics 

Table 7: Intel 8051 Read Cycle Timing Parameters (Busmode = 1)

Symbol

tsu1

th1

tpw1

tpd1

tdoz1

Parameter

Input Address Setup before /CE Active

Input Address and /CE Hold after /RE Inactive

/RE Active Duration

Delay from /RE Active to HI_DATA [7:0] Valid

Delay from /RE Inactive to HI_DATA[7:0] Tristate Mode

Min. Max. Unit

5

-

ns

5

-

ns

400 -

ns

-

40 ns

10

-

ns

HI_ADDR [4:0]

/CE

/RE

Valid

tsu1

th1

tpw1

HI_DATA[7:0]

tpd1

tdoz1

FIGURE 5: INTEL 8051 READ TIMING DIAGRAM

#This page is only for HDM8513AP.

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