PALCE20V8H-5 데이터 시트보기 (PDF) - Lattice Semiconductor

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PALCE20V8H-5

EE CMOS 24-Pin Universal Programmable Array Logic

Lattice Semiconductor 

The fixed OR array allows up to eight data product terms per output for logic functions. The

sum of these products feeds the output macrocell. Each macrocell can be programmed as

registered or combinatorial with an active-high or active-low output. The output configuration

is determined by two global bits and one local bit controlling four multiplexers in each

macrocell.

BLOCK DIAGRAM

I1 – I10

CLK/I0

10

Programmable AND Array

40 x 64

Input

Mux.

MACRO

MC0

MACRO

MC1

MACRO

MC2

MACRO

MC3

MACRO

MC4

MACRO

MC5

MACRO

MC6

MACRO

MC7

Input

Mux.

OE/I11 I12

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I13

16491E

FUNCTIONAL DESCRIPTION

The PALCE20V8 is a universal PAL device. It has eight independently configurable macrocells

(MC0-MC7). Each macrocell can be configured as a registered output, combinatorial output,

combinatorial I/O, or dedicated input. The programming matrix implements a programmable

AND logic array, which drives a fixed OR logic array. Buffers for device inputs have

complementary outputs to provide user-programmable input signal polarity. Pins 1 and 13 serve

either as array inputs or as clock (CLK) and output enable (OE) for all flip-flops.

Unused input pins should be tied directly to VCC or GND. Product terms with all bits

unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true

and complement of any input signal connected assume a logical LOW state.

The programmable functions on the PALCE20V8 are automatically configured from the user’s

design specification, which can be in a number of formats. The design specification is processed

2

PALCE20V8 Family

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