ADT7461 데이터 시트보기 (PDF) - Analog Devices

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ADT7461

±1°C Temperature Monitor with Series Resistance Cancellation

Analog Devices 

ADT7461

SPECIFICATIONS

TA = −40°C to +120°C, VDD = 3 V to 5.5 V, unless otherwise noted.

Table 1.

Parameter

POWER SUPPLY

Supply Voltage, VDD

Average Operating Supply Current, IDD

Undervoltage Lockout Threshold

Power-On-Reset Threshold

TEMPERATURE-TO-DIGITAL CONVERTER

Local Sensor Accuracy

Resolution

Remote Diode Sensor Accuracy

Resolution

Remote Sensor Source Current

Conversion Time

Maximum Series Resistance Cancelled

OPEN-DRAIN DIGITAL OUTPUTS

(THERM, ALERT/THERM2)

Output Low Voltage, VOL

High Level Output Leakage Current, IOH

ALERT Output Low Sink Current

SMBus INTERFACE3, 4

Logic Input High Voltage, VIH

SCLK, SDATA

Logic Input Low Voltage, VIL

SCLK, SDATA

Hysteresis

SMBus Output Low Sink Current

Logic Input Current, IIH, IIL

SMBus Input Capacitance, SCLK, SDATA

SMBus Clock Frequency

SMBus Timeout5

SCLK Falling Edge to SDATA Valid Time

Min Typ Max Unit Test Conditions

3.0 3.30 5.5 V

170 215 µA 0.0625 conversions/sec rate1

5.5 10 µA Standby mode , –40°C ≤ TA ≤ +85°C

5.5 20 µA Standby mode, +85°C ≤ TA ≤ +120°C

2.2 2.55 2.8 V

VDD input, disables ADC, rising edge

1

2.5 V

±1 ±3 °C

1

°C

±1 °C

±3 °C

0.25

°C

96

µA

36

µA

6

µA

32.13

114.6 ms

3.2

12.56 ms

3

kΩ

−40°C ≤ TA ≤ +100°C, 3 V ≤ VDD ≤ 3.6 V

+60°C ≤ TA ≤ +100°C, −55°C ≤ TD 2 ≤ +150°C, 3 V ≤ VDD ≤ 3.6 V

−40°C ≤ TA ≤ +120°C, −55°C ≤ TD 2 ≤ +150°C, 3 V ≤ VDD ≤ 5.5 V

High level3

Middle level3

Low level3

From stop bit to conversion complete (both channels), one-

shot mode with averaging switched on

One-shot mode with averaging off (i.e., conversion rate = 16,

32, or 64 conversions per second)

Resistance split evenly on both the D+ and D– inputs

0.4 V

IOUT = −6.0 mA3

0.1 1

µA

VOUT = VDD 3

1

mA ALERT forced to 0.4 V

2.1

V

3 V ≤ VDD ≤ 3.6 V

0.8 V

3 V ≤ VDD ≤ 3.6 V

500

mV

6

mA SDATA forced to 0.6 V

−1

+1 µA

5

pF

400 kHz

25 64 ms User programmable

1

µs Master clocking in data

1 See Table 8 for information on other conversion rates.

2 Guaranteed by characterization, but not production tested.

3 Guaranteed by design, but not production tested.

4 See SMBUS Timing Specifications section for more information.

5 Disabled by default. Details on how to enable it are in the SMBus section of this data sheet.

Rev. A | Page 3 of 24

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