CS5101A-AL8 데이터 시트보기 (PDF) - Cirrus Logic

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CS5101A-AL8

16-Bit, 100 kHz / 20kHz A/D Converters

Cirrus Logic 

CS5101A CS5102A

CLKIN

CRS/FIN

Internal

Status

Conv.

TRK1 or

TRK2

Min: 750 ns*

3.75 µs**

Coarse

Min: 1.125 µs*

6 clk

5.625 µs**

Fine Chg. Coarse

2 clk

Fine Chg.

Conv.

HOLD

* Applies to 5101A

** Applies to 5102A

Figure 2. Coarse-Charge/Fine-Charge Control

clock yields a maximum throughput of 20 kHz in

a single channel configuration.

Asynchronous Sampling Considerations

When HOLD goes low, the analog sample is cap-

tured immediately. The HOLD signal is latched

by the next falling edge of CLKIN, and conver-

sion then starts on the subsequent rising edge. If

HOLD is asynchronous to CLKIN, then there

will be a 1.5 CLKIN cycle uncertainty as to when

conversion starts. Considering the CS5101A with an

8 MHz CLKIN, with a 100 kHz HOLD signal, then

this 1.5 CLKIN uncertainty will result in a 1.5

CLKIN period possible reduction in fine charge time

for the next conversion.

Unipolar Input Offset Two’s

Bipolar Input

Voltage Binary Complement

Voltage

>(VREF-1.5 LSB) FFFF 7FFF >(VREF-1.5 LSB)

VREF-1.5 LSB FFFF

FFFE

7FFF

7FFE

VREF-1.5 LSB

VREF/2-0.5 LSB 8000

7FFF

0000

FFFF

-0.5 LSB

+0.5 LSB

0001

0000

8001

8000

-VREF+0.5 LSB

<(+0.5 LSB) 0000

8000 <(-VREF+0.5 LSB)

DS45F2

Table 1. Output Coding

This reduced fine charge time will be less than

the minimum specification. If the CLKIN fre-

quency is increased slightly (for example, to

8.192 MHz) then sufficient fine charge time will

always occur. The maximum frequency for

CLKIN is specified at 9.216 MHz; it is recom-

mended that for asynchronous operation at

100 kHz, CLKIN should be between 8.192 MHz

and 9.216 MHz.

Analog Input Range/Coding Format

The reference voltage directly defines the input

voltage range in both the unipolar and bipolar

configurations. In the unipolar configuration

(BP/UP low), the first code transition occurs 0.5

LSB above AGND, and the final code transition

occurs 1.5 LSB’s below VREF. In the bipolar

configuration (BP/UP high), the first code transi-

tion occurs 0.5 LSB above -VREF and the last

transition occurs 1.5 LSB’s below +VREF.

The CS5101A and CS5102A can output data in

either 2’s complement, or binary format. If the

CODE pin is high, the output is in 2’s comple-

ment format with a range of -32,768 to +32,767.

If the CODE pin is low, the output is in binary

format with a range of 0 to +65,535. See Table 1

for output coding.

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