L7400 데이터 시트보기 (PDF) - Intel
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L7400 Datasheet PDF : 91 Pages
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Low Power Features
2.1.2.6.1
2.1.2.6.2
Exit from the Deeper Sleep state or Intel Enhanced Deeper Sleep state is initiated by
DPRSTP# deassertion when either core requests a core state other than C4 or either
core requests a processor performance state other than the lowest operating point.
Intel Enhanced Deeper Sleep State
Intel Enhanced Deeper Sleep state is a sub-state of Deeper Sleep that extends power
saving capabilities by allowing the processor to further reduce core voltage once the L2
cache has been reduced to zero ways and completely shut down. The following events
occur when the processor enters Intel Enhanced Deeper Sleep state:
• The last core entering C4 issues a P_LVL4 I/O Read or an MWAIT(C4).
• The processor triggers a special chipset sequence to notify the chipset to redirect
all FSB traffic, except APIC messages, to memory. The snoops are replied as misses
by the chipset and are directed to main memory instead of the L2 cache.
• The processor will drive the VID code corresponding to the Intel Enhanced Deeper
Sleep state core voltage on the VID[6:0] pins.
Dynamic Cache Sizing
Dynamic Cache Sizing allows the processor to flush and disable a programmable
number of L2 cache ways upon each Deeper Sleep entry under the following
conditions:
• The second core is already in C4 and core sub-state Intel Enhanced Deeper Sleep
state is enabled (as specified in Section 2.1.2.6.1).
• The C0 timer, which tracks continuous residency in the Normal package state, has
not expired. This timer is cleared during the first entry into Deeper Sleep to allow
consecutive Deeper Sleep entries to shrink the L2 cache as needed.
• The FSB speed to processor core speed ratio is below the predefined L2 shrink
threshold.
If the FSB speed to processor core speed ratio is above the predefined L2 shrink
threshold, then L2 cache expansion will be requested. If the ratio is zero, then the ratio
will not be taken into account for Dynamic Cache Sizing decisions.
Upon STPCLK# deassertion, the first core exiting the Intel Enhanced Deeper Sleep
state will expand the L2 cache to 2 ways and invalidate previously disabled cache ways.
If the L2 cache reduction conditions stated above still exist when the last core returns
to C4 and the package enters Intel Enhanced Deeper Sleep state, then the L2 will be
shrunk to zero again. If a core requests a processor performance state resulting in a
higher ratio than the predefined L2 shrink threshold, the C0 timer expires, or the
second core (not the one currently entering the interrupt routine) requests the C1, C2,
or C3 states, then the whole L2 will be expanded when the next INTR event would
occur.
L2 cache shrink prevention may be enabled as needed on occasion through an
MWAIT(C4) sub-state field. If shrink prevention is enabled, then the Intel Core 2 Duo
mobile processor does not enter the Intel Enhanced Deeper Sleep state since the L2
cache remains valid and in full size.
Datasheet
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