M5M4V64S30ATP(1997) 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC

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M5M4V64S30ATP
(Rev.:1997)

64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM

MITSUBISHI ELECTRIC  

SDRAM (Rev.0.2)

Jan'97 Preliminary

MITSUBISHI LSIs

M5M4V64S30ATP-8, -10, -12

64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM

CLK

Command

Address

DQ

Read

Y

Q0 Q1 Q2 Q3

Write

Y

D0 D1 D2 D3

CL= 3

BL= 4

/CAS Latency

Burst Length

Burst Type

Burst Length

Initial Address BL

Column Addressing

A2 A1 A0

Sequential

Interleaved

00 0

0 1234 56 7 012 345 6 7

00 1

1 2345 67 0 103 254 7 6

01 0

2 3456 70 1 230 167 4 5

01 1

3 4567 01 2 321 076 5 4

8

10 0

4 5670 12 3 456 701 2 3

10 1

5 6701 23 4 547 610 3 2

11 0

6 7012 34 5 674 523 0 1

11 1

7 0123 45 6 765 432 1 0

- 00

0 123

012 3

- 01

1 230

4

- 10

2 301

103 2

230 1

- 11

3 012

321 0

-- 0

01

2

-- 1

10

01

10

MITSUBISHI ELECTRIC

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