M5M4V64S30ATP(1997) 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC

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M5M4V64S30ATP
(Rev.:1997)

64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM

MITSUBISHI ELECTRIC  

SDRAM (Rev.0.2)

Jan'97 Preliminary

MITSUBISHI LSIs

M5M4V64S30ATP-8, -10, -12

64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM

Multi Bank Interleaving READ (BL=4, CL=3)

CLK

Command

A0-9

ACT

Xa

tRCD

READ ACT

Y Xb

READ PRE

Y

A10

Xa

0

Xb

0

0

A11

Xa

Xb

BA0,1

00

00 10

10 00

DQ

Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2

/CAS latency

Burst Length

READ with Auto-Precharge (BL=4, CL=3)

CLK

Command

A0-9

A10

A11

BA0,1

DQ

ACT

Xa

tRCD

READ

Y

BL + tRP

ACT

BL

tRP

Xa

Xa

1

Xa

Xa

Xa

00

00

00

Qa0 Qa1 Qa2 Qa3

Internal precharge start

READ Auto-Precharge Timing (BL=4)

CLK

Command

ACT

CL=3 DQ

CL=2 DQ

READ

BL

Qa0 Qa1 Qa2 Qa3

Qa0 Qa1 Qa2 Qa3

Internal Precharge Start Timing

MITSUBISHI ELECTRIC

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