MC74HCU04A 데이터 시트보기 (PDF) - ON Semiconductor
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MC74HCU04A Datasheet PDF : 7 Pages
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MC74HCU04A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) (continued)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
–55 to
V
25_C
≤ 85_C ≤ 125_C Unit
VOL Maximum Low−Level Output
Voltage
Vin = VCC
|Iout| v 20 mA
2.0
0.2
0.2
0.2
V
4.5
0.5
0.5
0.5
6.0
0.5
0.5
0.5
Vin = VCC
|Iout| ≤ 2.4 mA 3.0
|Iout| ≤ 4.0 mA 4.5
|Iout| ≤ 5.2 mA 6.0
0.32
0.32
0.32
0.32
0.37
0.37
0.32
0.40
0.40
Iin
Maximum Input Leakage Current Vin = VCC or GND
ICC Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
6.0
±0.1
±1.0
±1.0
mA
6.0
1
10
40
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For VCC = 2.0 V, Vout = 0.2 V or VCC − 0.2 V.
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 2)
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
Cin Maximum Input Capacitance
Guaranteed Limit
VCC
–55 to
V
25_C
≤ 85_C ≤ 125_C Unit
2.0
70
3.0
40
4.5
14
6.0
12
90
105
ns
45
50
18
21
15
18
2.0
75
3.0
27
4.5
15
6.0
13
95
110
ns
32
36
19
22
16
19
−
10
10
10
pF
Typical @ 25°C, VCC = 5.0 V
CPD Power Dissipation Capacitance (Per Inverter)*
15
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
VCC
INPUT A
OUTPUT Y
tr
90%
50%
10%
tPHL
90%
50%
10%
tf
VCC
GND
tPLH
tTHL
tTLH
Figure 1. Switching Waveforms
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 2. Test Circuit
A
Y
Figure 3. Logic Detail
(1/6 of Device Shown)
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