MU9C2480A(1998) 데이터 시트보기 (PDF) - Music Semiconductors
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MU9C2480A Datasheet PDF : 28 Pages
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MU9C2480A/L
INSTRUCTION SET DESCRIPTIONS* Continued
accommodate the added features over the MU9C1480. Two
alternate sets of configuration registers can be selected by
using the Select Foreground and Select Background Registers
instructions. These registers are the Control, Segment Control,
Address, Mask Register 1, and the PS and PD registers. An
RSC instruction resets the Segment Control register count
values for both the Destination and Source counters to the
original Start limits. The Shift instructions shift the designated
register one bit right or left. The right and left limits for shifting
are determined by the CAM/RAM partitioning set in the
Control register. The Comparand register is a barrel-shifter,
and for the example of a device set to 64 bits of CAM executing
a Shift Comparand Right instruction, bit 0 is moved to bit 63,
bit 1 is moved to bit 0, and bit 63 is moved to bit 62. For a Shift
Comparand Left instruction, bit 63 is moved to bit 0, bit 0 is
moved to bit 1, and bit 62 is moved to bit 63. MR2 acts as a
sliding mask, where for a Shift Right instruction bit 1 is moved
to bit 0, while bit 0 “falls off the end,” and bit 63 is replicated to
bit 62. For a Shift Mask Left instruction, bit 0 is replicated to bit
1, bit 62 is moved to bit 63, and bit 63 “falls off the end.” With
shorter width CAM fields, the bit limits on the right or left
move to match the width of CAM field.
Instruction: Set Full Flag (SFF)
Binary Op-Code: 0000 0111 0000 0000
The SFF instruction is a special instruction used to force the
Full flag LOW to permit setting the Page Address register in
vertically cascaded systems.
Instruction: No Operation (NOP)
Binary Op-Code: 0000 0011 0000 0000
The NOP (No-OP) belongs to the MOV instructions, where a
register is moved to itself. No change occurs within the device.
This instruction is useful in unlocking the daisy chain in
Standard mode.
Notes:
* Instruction cycle lengths given in Table 7 on page 21.
† If f=1, the instruction requires an absolute address to be supplied
on the following cycle as a Command write. The value supplied on
the second cycle of the instruction will update the address register.
After operations involving M@[AR] or M@aaaH, the Address
register will increment or decrement depending on the setting in the
Control register.
INSTRUCTION SET SUMMARY
MNEMONIC FORMAT
INS dst,src[msk],val
INS: Instruction mnemonic
dst: Destination of the data
src: Source of the data
msk: Mask register used
val: Validity condition set at the location written
Instruction: Select Persistent Destination Cont.
Operation
Mnemonic Op-Code
Mem. at Addr. Reg. set Empty SPD M@[AR],E
0125H
Masked by MR1
SPD M@[AR][MR1],E 0165H
Masked by MR2
SPD M@[AR][MR2],E 01A5H
Mem. at Addr. Reg. set Skip
Masked by MR1
Masked by MR2
SPD M@[AR],S
0126H
SPD M@[AR][MR1],S 0166H
SPD M@[AR][MR2],S 01A6H
Instruction: Select Persistent Source
Operation
Mnemonic Op-Code
Comparand Register
SPS CR
0000H
Mask Register 1
SPS MR1
0001H
Mask Register 2
SPS MR2
0002H
Memory Array at Addr. Reg. SPS M@[AR]
0004H
Memory Array at Address
SPS M@aaaH
0804H
Mem. at Highest-Prio. Match SPS M@HM
0005H
Instruction: Select Persistent Destination
Operation
Mnemonic Op-Code
Comparand Register
SPD CR
0100H
Masked by MR1
SPD CR[MR1]
0140H
Masked by MR2
SPD CR[MR2]
0180H
Mask Register 1
Mask Register 2
Mem. at Addr. Reg. set Valid
Masked by MR1
Masked by MR2
SPD MR1
0108H
SPD MR2
0110H
SPD M@[AR],V
0124H
SPD M@[AR][MR1],V 0164H
SPD M@[AR][MR2],V 01A4H
Mem. at Addr. Reg. set Random SPD M@[AR],R
0127H
Masked by MR1
SPD M@[AR][MR1],R 0167H
Masked by MR2
SPD M@[AR][MR2],R 01A7H
Memory at Address set Valid SPD M@aaaH,V
0924H
Masked by MR1
SPD M@aaaH[MR1],V 0964H
Masked by MR2
SPD M@aaaH[MR2],V09A4H
Memory at Addr. set Empty
Masked by MR1
Masked by MR2
SPD M@aaaH,E
0925H
SPD M@aaaH[MR1],E 0965H
SPD M@aaaH[MR2],E 09A5H
Memory at Address set Skip
Masked by MR1
Masked by MR2
SPD M@aaaH,S
0926H
SPD M@aaaH[MR1],S 0966H
SPD M@aaaH[MR2],S 09A6H
Mem. at Address set Random SPD M@aaaH,R
0927H
Masked by MR1
SPD M@aaaH[MR1],R 0967H
Masked by MR2
SPD M@aaaH[MR2],R 09A7H
Mem. at Highest-Prio. Match, Valid SPD M@HM,V
012CH
Masked by MR1
SPD M@HM[MR1],V 016CH
Masked by MR2
SPD M@HM[MR2],V 01ACH
Rev. 1a
18
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