PIN ASSIGNMENTS
VRHS 1
VRLF 2
VRLS 3
VRLT 4
AGND 5
VINA 6
AGND 7
VINB 8
VDD 9
VCAL 10
AGND 11
VINC 12
AGND 13
39 CLK
38 DB9
37 DB8
36 DB7
35 DB6
34 DB5
33 DB4
32 DB3
31 DB2
30 DB1
29 DB0
28 DAV
27 OVDD
PIN FUNCTIONS
Name
Function
VINA
VINB
Analog input for channel A
Analog input for channel B
VINC
Analog input for channel C
DA0–DA9 CMOS-compatible digital output data for channel A
(+2.7 V to +5.0 voltage logic)
DB0–DB9 CMOS-compatible digital output data for channel B
(+2.7 V to +5.0 voltage logic)
DC0–DC9 CMOS-compatible digital output data for channel C
(+2.7 V to +5.0 voltage logic)
OEN
Output enable pin. (Low = enabled; High = high
impedance)
CLK
CMOS-compatible input clock (2x of sample rate).
VRHF
Input for top of reference ladder (force)
VRHS
Input for top of reference ladder (sense)
VRLF
Input for bottom of reference ladder (force)
VRLS
VDD
Input for bottom of reference ladder (sense)
Analog +5 V; Digital +5 V
OVDD
Output supply +2.7 / +5 V
AGND Analog ground
DGND Digital ground
VRLT
Tie to VRLS
VCAL
Calibration reference
DAV
Data available
ORDERING INFORMATION
PART NUMBER
SPT7853SCT
TEMPERATURE RANGE
0 to +70 °C
PACKAGE TYPE
52-Pin TQFP
SPT7853
10
12/14/99