MTD502EF 데이터 시트보기 (PDF) - Unspecified

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MTD502EF

2 Port 10M/100M Switch With Build_in Memory

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MYSON

TECHNOLOGY

MTD502E

MTD502EG(80LQFP) Pin Definition Mapping Under Different Configurations

Pin No. I/O

MII Phy_MII Rmii Phy_Rm

mode mode mode ii mode

Descriptions

56

IO LnAc0_D LnAc0_D LnAc0_D LnAc0_D Port0: Link_Activity LED display,

low_active. *

when in Link_On state : this LED pin is

always in low_active.

when have Tx or Rx activity in this port

: this LED pin present port0’s Tx/Rx

activity, using flash style for display.

57

IO LnRx1_D LnRx1_D LnRx1_D LnRx1_D Port1: Link_Rx LED display,

low_active. *

when in Link_On state : this LED pin is

always in low_active.

when have Rx activity in this port : this

LED pin present port1’s Rx activity,

using flash style for display.

58

IO LnRx0_D LnRx0_D LnRx0_D LnRx0_D Port0: Link_Rx LED display,

low_active. *

when in Link_On state : this LED pin is

always in low_active.

when have Rx activity in this port : this

LED pin present port0’s Rx activity,

using flash style for display.

59-61 IO (NC) (NC) (NC) (NC)

62

VCC

63

IO (NC) (NC) (NC) (NC)

64

GND

65-69 IO (NC) (NC) (NC) (NC)

70

IO (NC) P0MDIO (NC) P0MDIO

71

IO (NC) P0MDC (NC) P0MDC

72

O CLK25O CLK25O CLK25O CLK25O clock 25Mhz output.

73

VCC

74

I SYSCLK SYSCLK SYSCLK SYSCLK system clock input, 50Mhz operation.

75

IO (NC) (NC) (NC) (NC)

76

I RSTB RSTB RSTB RSTB system resetb input, low_active.

77

I LINK0 (NC) LINK0 (NC)

78

O TXD0_3 RXD0_3 (NC) (NC)

79

VCC

80

O TXD0_2 RXD0_2 (NC) (NC)

note: input signal LINK,SPEED,FULL from PHY device are low_active definnition.

13/20

MTD502E Revision 1.3 12/07/2000

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