M68Z512 데이터 시트보기 (PDF) - STMicroelectronics
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M68Z512 Datasheet PDF : 16 Pages
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M68Z512
4 Mbit (512 Kbit x 8) Low Power SRAM with Output Enable
FEATURES SUMMARY
s ULTRA LOW DATA RETENTION CURRENT
– 100nA (typical)
– 10µA (max)
s OPERATION VOLTAGE: 5.0V ± 10%
s 512 Kbit x 8 SRAM WITH OUTPUT ENABLE
s EQUAL CYCLE and ACCESS TIMES: 70ns
s LOW VCC DATA RETENTION: 2.0V
s TRI-STATE COMMON I/O
s CMOS FOR OPTIMUM SPEED/POWER
s AUTOMATIC POWER-DOWN WHEN
DESELECTED
s INTENDED FOR USE WITH ST
ZEROPOWER® AND TIMEKEEPER®
CONTROLLERS
Figure 1. Package
32
1
TSOP II 32 (NC)
10 x 20mm
May 2002
1/15
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