MK10DX2M0AVFM12 데이터 시트보기 (PDF) - Freescale Semiconductor
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MK10DX2M0AVFM12 Datasheet PDF : 79 Pages
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Pinout
8.1 K10 signal multiplexing and pin assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
144 144 Pin Name Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
LQFP MAP
BGA
— L5 RTC_
RTC_
RTC_
WAKEUP_B WAKEUP_B WAKEUP_B
— M5 NC
NC
NC
— A10 NC
NC
NC
— B10 NC
NC
NC
— C10 NC
NC
NC
1 D3 PTE0
ADC1_SE4a ADC1_SE4a PTE0
SPI1_PCS1 UART1_TX SDHC0_D1
I2C1_SDA RTC_CLKOUT
2 D2 PTE1/
ADC1_SE5a ADC1_SE5a PTE1/
SPI1_SOUT UART1_RX SDHC0_D0
LLWU_P0
LLWU_P0
I2C1_SCL SPI1_SIN
3 D1 PTE2/
ADC1_SE6a ADC1_SE6a PTE2/
SPI1_SCK UART1_CTS_ SDHC0_DCLK
LLWU_P1
LLWU_P1
b
4 E4 PTE3
ADC1_SE7a ADC1_SE7a PTE3
SPI1_SIN
UART1_RTS_ SDHC0_CMD
b
SPI1_SOUT
5 E5 VDD
VDD
VDD
6 F6 VSS
VSS
VSS
7 E3 PTE4/
DISABLED
LLWU_P2
PTE4/
LLWU_P2
SPI1_PCS0 UART3_TX SDHC0_D3
8 E2 PTE5
DISABLED
PTE5
SPI1_PCS2 UART3_RX SDHC0_D2
9 E1 PTE6
DISABLED
PTE6
SPI1_PCS3 UART3_CTS_ I2S0_MCLK
b
10 F4 PTE7
DISABLED
PTE7
UART3_RTS_ I2S0_RXD0
b
11 F3 PTE8
DISABLED
PTE8
I2S0_RXD1 UART5_TX I2S0_RX_FS
12 F2 PTE9
DISABLED
PTE9
I2S0_TXD1 UART5_RX I2S0_RX_
BCLK
13 F1 PTE10
DISABLED
PTE10
UART5_CTS_ I2S0_TXD0
b
14 G4 PTE11
DISABLED
PTE11
UART5_RTS_ I2S0_TX_FS
b
15 G3 PTE12
DISABLED
PTE12
I2S0_TX_
BCLK
16 E6 VDD
VDD
VDD
17 F7 VSS
VSS
VSS
18 H1 PTE16
ADC0_SE4a ADC0_SE4a PTE16
SPI0_PCS0 UART2_TX FTM_CLKIN0
FTM0_FLT3
19 H2 PTE17
ADC0_SE5a ADC0_SE5a PTE17
SPI0_SCK UART2_RX FTM_CLKIN1
LPTMR0_
ALT3
20 G1 PTE18
ADC0_SE6a ADC0_SE6a PTE18
SPI0_SOUT UART2_CTS_ I2C0_SDA
b
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
70
Freescale Semiconductor, Inc.
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