MACH111-18JC/1 데이터 시트보기 (PDF) - Lattice Semiconductor

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MACH111-18JC/1

High-Performance EE CMOS Programmable Logic

Lattice Semiconductor 

44-PIN TQFP CONNECTION DIAGRAM (MACH211-7/10/12/15 AND

MACH211SP-6/7/10/12/15)

Top View

44-Pin TQFP

Block A

Block D

I/O5

1

I/O6

2

I/O7

3

(TDI) I0

4

(CLK 0/I0) CLK0/I1

5

GND

6

(TCK) CLK1/I2

7

I/O8

8

I/O9

9

I/O10

10

I/O11

11

33

I/O27

32

I/O26

31

I/O25

30

I/O24

29

CLK3/I5 (TDO)

28

GND

27

CLK2/I4 (CLK 1/I1)

26

I3 (TMS)

25

I/O23

24

I/O22

23

I/O21

Block B

Block C

PIN DESIGNATIONS

CLK/I = Clock or Input

GND = Ground

I

= Input

I/O = Input/Output

VCC = Supply Voltage

Note:

1. Pin designators in parentheses ( ) apply to the MACH211SP

TDI = Test Data In

TCK = Test Clock

TMS = Test Mode Select

TDO = Test Data Out

14051K-024

MACH 1 & 2 Families

41

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