MACH111-18JC/1 데이터 시트보기 (PDF) - Lattice Semiconductor

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MACH111-18JC/1

High-Performance EE CMOS Programmable Logic

Lattice Semiconductor 

84-PIN PLCC CONNECTION DIAGRAM (MACH231-6/7/10/12/15)

Top View

84-Pin PLCC

Block A

Block H

I/O8

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

CLK0/I0

VCC

GND

CLK1/I1

I/O16

I/O17

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

GND

11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75

12

74

13

73

14

72

15

71

16

70

17

69

18

68

19

67

20

66

21

65

22

64

23

63

24

62

25

61

26

60

27

59

28

58

29

57

30

56

31

55

32

54

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 5253

GND

I/O55

I/O54

I/O53

I/O52

I/O51

I/O50

I/O49

I/O48

CLK3/I4

GND

VCC

CLK2/I3

I/O47

I/O46

I/O45

I/O44

I/O43

I/O42

I/O41

I/O40

Block D

PIN DESIGNATIONS

CLK/I = Clock or Input

GND = Ground

I

= Input

I/O = Input/Output

VCC = Supply Voltage

Block E

14051K-027

44

MACH 1 & 2 Families

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