IDT71V321L 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT71V321L Datasheet PDF : 15 Pages
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IDT71V321S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts
Truth Tables
Table I — Non-Contention
Read/Write Control(4)
Left or Right Port(1)
R/W CE OE
D0-7
Function
X
H
X
Z
Port Deselected and in Power-
Down Mode. ISB2 or ISB4
X
H
X
Z
CER = CEL = VIH, Power-Down Mode ISB1
or ISB3
L
L
X
DATAIN Data on Port Written Into Memory(2)
H
L
L
DATAOUT Data in Memory Output on Port(3)
H
L
H
Z
High-impedance Outputs
NOTES:
1. A0L – A10L ≠ A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = High-impedance.
3026 tbl 13
Table II — Interrupt Flag(1,4)
Left Port
R/WL
CEL
OEL
A10L-A0L
INTL
R/WR
CER
L
L
X
7FF
X
X
X
X
X
X
X
X
X
L
X
X
X
X
L(3)
L
L
X
L
L
7FE
H(2)
X
X
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH, 'L' = LOW, 'X' = DON’T CARE
Table III — Address BUSY Arbitration
Inputs
Outputs
CEL CER
AOL-A10L
AOR-A10R
BUSYL(1) BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
HX
MATCH
H
H
Normal
XH
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
NOTES:
3026 tbl 15
1. PinsBUSYLandBUSYR arebothoutputs. BUSYX outputsontheIDT71V321aretotem-
pole.
2. 'L'iftheinputstotheoppositeportwerestablepriortotheaddressandenableinputsofthis
port. 'H' if the inputs to the opposite port became stable after the address and enable inputs
of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR
outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level
on the pin.
Industrial and Commercial Temperature Ranges
Right Port
OER
A10R-A0R
X
X
L
7FF
X
7FE
X
X
INTR
Function
L(2) Set Right INTR Flag
H(3) Reset Right INTR Flag
X Set Left INTL Flag
X Reset Left INTL Flag
3026 tbl 14
61.422
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