T7256A 데이터 시트보기 (PDF) - Agere -> LSI Corporation

부품명

상세내역

제조사

T7256A

Compliance with the New ETSI PSD Requirement

Agere -> LSI Corporation 

Data Sheet

January 1998

T7256 Single-Chip NT1 (SCNT1) Transceiver

Microprocessor Interface Description (continued)

Registers (continued)

Table 7. Data Flow Control—U and S/T B Channels (Address 03h)

Reg

R/W

DFR0

R/W

Default State on RESET

Bit 7

SXB21

1

Bit 6

SXB20

1

Bit 5

SXB11

1

Bit 4

SXB10

1

Bit 3

UXB21

1

Bit 2

UXB20

1

Bit 1

UXB11

1

Bit 0

UXB10

1

Register Bit

DFR0 1—0

DFR0 3—2

DFR0 5—4

DFR0 7—6

Symbol

UXB1[1:0]

UXB2[1:0]

SXB1[1:0]

SXB2[1:0]

Name/Description

U-Interface Transmit Path Source for B1 Channel. Refer to point #1

in Figure 16.

00—Not used.

01—TDM bus.

10—All 1s.

11—S/T-interface receive (default).

U-Interface Transmit Path Source for B2 Channel. Refer to point #1

in Figure 16.

00—Not used.

01—TDM bus.

10—All 1s.

11—S/T-interface receive (default).

S/T-Interface Transmit Path Source for B1 Channel. Refer to point #2

in Figure 16.

00—Not used.

01—TDM bus.

10—S/T-interface receive (ITU-T I.430 Loop C for B1 channel).

11—U-interface receive (default).

S/T-Interface Transmit Path Source for B2 Channel. Refer to point #2

in Figure 16.

00—Not used.

01—TDM bus.

10—S/T-interface receive (ITU-T I.430 Loop C for B2 channel).

11—U-Interface receive (default).

Lucent Technologies Inc.

25

Share Link: