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T7256A

Compliance with the New ETSI PSD Requirement

Agere -> LSI Corporation 

Data Sheet

January 1998

T7256 Single-Chip NT1 (SCNT1) Transceiver

Microprocessor Interface Description (continued)

Registers (continued)

Table 9. TDM Bus Timing Control (Address 05h)

Bits 0—4 are enabled only if TDMEN = 0 (register GR2, bit 5) and one or more of bits DFR1[2:7] are set to 0.

Reg

R/W

TDR0

R/W

Default State on RESET

Bit 7

—

—

Bit 6

—

—

Bit 5

—

—

Bit 4

—

—

Bit 3

FSP

1

Bit 2

FSC2

1

Bit 1

FSC1

1

Bit 0

FSC0

1

Register Bit

TDR0 2—0

TDR0

3

Symbol

FSC[2:0]

FSP

Name/Description

Frame Strobe (FS) Control. Selects location of strobe envelope within

TDM bus time slots.

000—S/T-interface 2B+D channel strobe (18-bit envelope).

001—U-interface 2B+D channel strobe (18-bit envelope).

010—S/T-interface B2 channel strobe (8-bit envelope).

011—U-interface B2 channel strobe (8-bit envelope).

100—S/T-interface D channel strobe (2-bit envelope).

101—U-interface D channel strobe (2-bit envelope).

110—S/T-interface B1 channel strobe (8-bit envelope).

111—U-interface B1 channel strobe (8-bit envelope) (default).

Frame Strobe (FS) Polarity.

0—Active-low envelope.

1—Active-high envelope (default).

Lucent Technologies Inc.

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