MAX2165 데이터 시트보기 (PDF) - Maxim Integrated
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MAX2165 Datasheet PDF : 24 Pages
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Single-Conversion DVB-H Tuner
START
WRITE DEVICE
ADDRESS
110000[ADDR]
R/W
ACK
WRITE REGISTER
ADDRESS
ACK
0
0x00
WRITE DATA TO
REGISTER 0x00
ACK
0x0E
WRITE DATA TO
REGISTER 0x01
0xD8
ACK
WRITE DATA TO
REGISTER 0x02
ACK
STOP
0xE1
Figure 2. Example of Writing Registers 0 Through 2 with 0x0E, 0xDS, and 0xE1, Respectively
START
WRITE DEVICE
ADDRESS
110000[ADDR]
R/W
ACK
WRITE 1st REGISTER
ADDRESS
ACK
START
WRITE DEVICE
ADDRESS
0
00000000
110000[ADDR]
R/W
ACK
WRITE DATA
REG 0
ACK
WRITE DATA
REG 1
NACK
STOP
1
D7–D0
D7–D0
Figure 3. Example of Reading Data from Registers 0 Through 2
A write cycle begins with the bus master issuing a START
condition followed by the 7 slave address bits and a write
bit (R/W = 0). The MAX2165 issues an ACK if the slave
address byte is successfully received. The bus master
must then send to the slave the address of the first regis-
ter it wishes to write to (see Table 1 for register address-
es). If the slave acknowledges the address, the master
can then write one byte to the register at the specified
address. Data is written beginning with the most signifi-
cant bit and is clocked in on the rising edge of SCLK. The
MAX2165 again issues an ACK if the data is successfully
written to the register. The master can continue to write
data to the successive internal registers with the
MAX2165 acknowledging each successful transfer, or it
can terminate transmission by issuing a STOP condition.
The write cycle does not terminate until the master issues
a STOP condition.
Figure 2 illustrates an example in which registers 0 through
2 are written with 0x0E, 0xD8, and 0xE1, respectively.
Read Cycle
All registers on the MAX2165 are available to be read by
the master with 3 of the registers being read-only.
A read cycle begins with the bus master issuing a
START condition followed by the 7 slave address bits
and a write bit (R/W = 0). The MAX2165 issues an ACK
if the slave address byte is successfully received. The
master then sends the address of the first register that it
wishes to read. The MAX2165 then issues another ACK.
Next, the master must issue a START condition followed
by the 7 slave address bits and a read bit (R/W = 1).
The MAX2165 issues an ACK if it successfully recog-
nizes its address and begins sending data from the
specified register address starting with the most signifi-
cant bit (MSB). Data is clocked out of the MAX2165 on
the rising edge of SCLK. On the 9th rising edge of
SCLK, the master can issue an ACK and continue read-
ing successive registers, or it can issue a NACK fol-
lowed by a STOP condition to terminate transmission.
The read cycle does not terminate until the master
issues a STOP condition. Figure 3 illustrates an exam-
ple in which registers 0 and 1 are read back.
Applications Information
RF Input
The RF input is internally matched and provides good
return loss over the entire band of operation for either 50Ω
or 75Ω systems, and requires a DC-blocking capacitor.
RF and Baseband Gain Control
The MAX2165 features separate RF and baseband gain-
control inputs that can be used to achieve optimum SNR
over a wide input dynamic range. Baseband gain control
is achieved through the BB_AGC pin. This pin is typically
controlled by the baseband processor and can accept
voltages from 0.4V to 2.3V with 2.3V providing maximum
baseband gain.
RF gain control is achieved through the RF_AGC pin. This
pin also accepts control voltages from 0.4V to 2.3V with
2.3V providing maximum RF gain. Closed-loop automatic
RF gain control can be achieved by connecting the
OVLD_DET pin through a lowpass filter to the RF_AGC
pin. See the IF Power Detector section.
The RF signal path features a low-noise amplifer (LNA)
that can be switched in an out-of-signal path. Program
the LNASW bit in the LNA register (Table 7) to 1 to enable
the LNA. Enabling the LNA adds about 17mA of current,
16dB of gain, and causes less than 10° of phase change
in the received signal.
IF Power Detector
The MAX2165 baseband power detector compares the
total weighted received input signal within approximately
2 channels of the wanted channel to a programmable
threshold. This threshold can be programmed to differ-
ent values with the PD_TH[2:0] bits in the baseband
control register.
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