MX97103FC 데이터 시트보기 (PDF) - Macronix International
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MX97103FC Datasheet PDF : 13 Pages
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PIN CONFIGURATION
MX97103
AD14
81
VSS
82
AD13
83
AD12
84
VDD
85
AD11
86
AD10
87
VSS
88
AD9
89
AD8
90
VSS
91
CBE0#
92
AD7
93
AD6
94
VSS
95
AD5
96
AD4
97
VDD
98
AD3
99
AD2
100
MX97103
50
VDD
49
AD26
48
AD17
47
VSS
46
AD28
45
AD29
44
VSS
43
AD30
42
AD31
41
VDD
40
CLK
39
VSS
38
RST#
37
INTA#
36
AVDD(C)
35
SX2
34
SX1
33
AVDDX
32
AVDD(P)
31
AVSS(P+X)
BLOCK DIAGRAM
S/T Interface
Transmitter
Multiframe Activation/
control Deactivation
Receiver
7.68MHZ
OSC
DPLL
GCI interface
DU DD
GCI
DCL FSC1
LAP-D&B-HDLC
B-channel
Switching
FIFOS
PCI
Interface
EEPROM
Interface
PCI bus
P/N:PM0564
REV. 1.0, FEB. 23, 1999
2
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