CY7C1461AV33(2008) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1461AV33
(Rev.:2008)
(Rev.:2008)
Cypress Semiconductor
CY7C1461AV33 Datasheet PDF : 32 Pages
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CY7C1461AV33
CY7C1463AV33, CY7C1465AV33
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage on VDD Relative to GND ........–0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD
DC Voltage Applied to Outputs
in Tri-State ...........................................–0.5V to VDDQ + 0.5V
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Latch Up Current .................................................... >200 mA
Operating Range
Range
Ambient
Temperature
VDD
VDDQ
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5%
Industrial –40°C to +85°C
to VDD
Electrical Characteristics
Over the Operating Range[16, 17]
Parameter
Description
Test Conditions
VDD
VDDQ
Power Supply Voltage
IO Supply Voltage
for 3.3V IO
for 2.5V IO
VOH
Output HIGH Voltage for 3.3V IO, IOH = –4.0 mA
for 2.5V IO, IOH = –1.0 mA
VOL
Output LOW Voltage for 3.3V IO, IOL = 8.0 mA
for 2.5V IO, IOL = 1.0 mA
VIH
Input HIGH Voltage[16] for 3.3V IO
for 2.5V IO
VIL
Input LOW Voltage[16] for 3.3V IO
for 2.5V IO
IX
Input Leakage Current GND ≤ VI ≤ VDDQ
except ZZ and MODE
Input Current of MODE Input = VSS
Input = VDD
Input Current of ZZ
Input = VSS
Input = VDD
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply VDD = Max, IOUT = 0 mA,
7.5 ns cycle, 133 MHz
Current
f = fMAX = 1/tCYC
10 ns cycle, 100 MHz
ISB1
Automatic CE
VDD = Max, Device Deselected, 7.5 ns cycle, 133 MHz
Power Down
VIN ≥ VIH or VIN ≤ VIL
10 ns cycle, 100 MHz
Current—TTL Inputs f = fMAX, Inputs Switching
ISB2
Automatic CE
VDD = Max, Device Deselected, All speeds
Power Down
VIN ≤ 0.3V or VIN > VDD – 0.3V,
Current—CMOS Inputs f = 0, Inputs Static
ISB3
Automatic CE
VDD = Max, Device Deselected, 7.5 ns cycle, 133 MHz
Power Down
or VIN ≤ 0.3V or VIN > VDDQ – 0.3V 10 ns cycle, 100 MHz
Current—CMOS Inputs f = fMAX, Inputs Switching
ISB4
Automatic CE
VDD = Max, Device Deselected, All Speeds
Power Down
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
Current—TTL Inputs f = 0, Inputs Static
Min
3.135
3.135
2.375
2.4
2.0
2.0
1.7
–0.3
–0.3
–5
–30
–5
–5
Max Unit
3.6
V
VDD
V
2.625 V
V
V
0.4
V
0.4
V
VDD + 0.3V V
VDD + 0.3V V
0.8
V
0.7
V
5
μA
μA
5
μA
μA
30
μA
5
μA
310 mA
290 mA
180 mA
180 mA
120 mA
180 mA
180 mA
135 mA
Notes
16. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
17. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05356 Rev. *G
Page 21 of 32
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