CY7C1461AV33(2008) 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C1461AV33
(Rev.:2008)

36 Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture

Cypress Semiconductor 

CY7C1461AV33

CY7C1463AV33, CY7C1465AV33

Document History Page

Document Title: CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 36 Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through

SRAM with NoBL™ Architecture

Document Number: 38-05356

REV. ECN NO.

Issue

Date

Orig. of

Change

Description of Change

** 254911 See ECN SYT New data sheet

Part number changed from previous revision. New and old part number differ by

the letter “A”

*A 300131 See ECN SYT Removed 150- and 117-MHz Speed Bins

Changed ΘJA and ΘJC from TBD to 25.21 and 2.58 °C/W, respectively, for TQFP

package

Added Pb-free information for 100-pin TQFP, 165 FBGA and 209 FBGA packages

Added “Pb-free BG and BZ packages availability” below the Ordering Information

*B

320813 See ECN

SYT Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209 FBGA

Changed the test condition from VDD = Min. to VDD = Max for VOL in the Electrical

Characteristics table

Replaced the TBD’s for IDD, ISB1, ISB2, ISB3 and ISB4 to their respective values

Replaced TBD’s for ΘJA and ΘJC to their respective values on the Thermal Resis-

tance table for 165 FBGA and 209 FBGA Packages

Changed CIN, CCLK and CIO to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP

Package

Removed “Pb-free BG packages availability” comment below the Ordering Infor-

mation

*C 331551 See ECN SYT Modified Address Expansion balls in the pinouts for 165 FBGA and 209 FBGA

Packages according to JEDEC standards and updated the Pin Definitions accord-

ingly

Modified VOL, VOH test conditions

Replaced TBD to 100 mA for IDDZZ

Changed CIN, CCLK and CIO to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA

Package

Added Industrial Temperature Grade

Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively

Updated the Ordering Information by shading and unshading MPNs according to

availability

*D 417547 See ECN RXU Converted from Preliminary to Final

Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901

North First Street” to “198 Champion Court”

Changed IX current value in MODE from –5 & 30 μA to –30 & 5 μA respectively

and also Changed IX current value in ZZ from –30 & 5 μA to –5 & 30 μA respectively

on page# 20

Modified test condition from VIH < VDD to VIH < VDD

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

Electrical Characteristics Table

Replaced Package Name column with Package Diagram in the Ordering

Information table

Replaced Package Diagram of 51-85050 from *A to *B

Updated the Ordering Information

Document #: 38-05356 Rev. *G

Page 31 of 32

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