NXP Semiconductors
HEF40174B
Hex D-type flip-flop
6. Pinning information
6.1 Pinning
Fig 3. Pin configuration
HEF40174B
MR 1
Q0 2
D0 3
D1 4
Q1 5
D2 6
Q2 7
VSS 8
16 VDD
15 Q5
14 D5
13 D4
12 Q4
11 D3
10 Q3
9 CP
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6.2 Pin description
Table 2. Pin description
Symbol
Pin
MR
1
Q0, Q1, Q2, Q3, Q4, Q5 2, 5, 7, 10, 12, 15
D0, D1, D2, D3, D4, D5 3, 4, 6, 11, 13, 14
VSS
8
CP
9
VDD
16
7. Functional description
Description
master reset input (active LOW)
buffered output
data input
ground supply voltage
clock input (LOW-to-HIGH; edge-triggered)
supply voltage
Table 3.
Input
CP
X
Function table[1]
D
H
L
X
X
Output
MR
Q
H
H
H
L
H
no change
L
L
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; = positive-going transition; = negative-going transition.
HEF40174B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
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