HEF4043B-Q100 데이터 시트보기 (PDF) - NXP Semiconductors.

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HEF4043B-Q100

Quad R/S latch with 3-state outputs

NXP Semiconductors. 

NXP Semiconductors

HEF4043B-Q100

Quad R/S latch with 3-state outputs

Table 8. Dynamic power dissipation PD

PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; Tamb = 25 C.

Symbol Parameter

VDD

Typical formula for PD (W)

where:

PD

dynamic power 5 V

PD = 1100  fi + (fo  CL)  VDD2

fi = input frequency in MHz;

dissipation

10 V

PD = 4400  fi + (fo  CL)  VDD2

fo = output frequency in MHz;

15 V

PD = 11400  fi + (fo  CL)  VDD2

CL = output load capacitance in pF;

VDD = supply voltage in V;

(fo  CL) = sum of the outputs.

12. Waveforms

tr

tf

VI

90 %

input nS

0 V 10 %

VM

tW

VI

input nR

0V

VOH

output nQ

VOL

10 %

tPLH

90 %

VM

tTLH

VM

tW

tPHL

tTHL

001aai286

Fig 4.

tr and tf are the input rise and fall times.

Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.

Transition times: transition time (tt) = HIGH LOW (tTHL) or LOW HIGH (tTLH) transition times.

Measurement points are given in Table 9 and test data is given in Table 10.

Input minimum set (nS) and reset (nR) pulse widths, inputs nS or nR to latch output (nQ) propagation

delay and nQ transition time

HEF4043B_Q100

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 15 July 2013

© NXP B.V. 2013. All rights reserved.

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