ADP3808JCPZ-RL 데이터 시트보기 (PDF) - ON Semiconductor
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ADP3808JCPZ-RL Datasheet PDF : 15 Pages
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ADP3808A
ELECTRICAL CHARACTERISTICS
VCC = 20 V, EN = 5.0 V, REFIN = 3.0 V, TA = 0°C to 100°C; unless otherwise noted. (Note 1)
Parameter
Symbols
Symbol
Min
Typ
Max Unit
LIMIT Propagation Delay Time
tpdl(LIMIT)
(SYSP) − (SYSM) rising > 55 mV to
LIMIT going low
1
ms
EXTPWR Current Threshold
EXTPWR Voltage Threshold
EXTPWR Output Voltage Low
EXTPWR Propagation Delay
Time
VTH(EXTPWR)
VTH(EXTPWR)
VTH(EXTPWR)
Vdpl(EXTPWR)
SYSP to SYSM
SYSP to AGND
IEXTPWR = −100 mA
SYSP Rising > 18.5 V to EXTPWR
going low
17.5
22.5
27.5
mV
18.0 18.25 18.5
V
5
50
mV
1
ms
Oscillator
Maximum Frequency
Frequency Variation
RT Output Voltage
Zero Duty Cycle Threshold
Maximum Duty Cycle Threshold
fOSC
ΔfOSC
VRT
RT = 150 kW
Measured at COMP
Measured at COMP
1
MHz
250
290
340 kHz
1.9
2
2.1
V
1
V
2
V
Logic Inputs (EN, CELLSEL)
Input Voltage High
Input Voltage Low
Input Current
High−Side Driver
Output Resistance, Sourcing
Current
VIH
VIL
IIN
Inputs = 0 V or 5 V
BST to SW = 5 V
2.0
V
0.8
V
–1
+1
mA
3
8
W
Output Resistance, Sinking
Current
BST to SW = 5 V
3
8
W
Output Resistance, Unbiased
Transition Time
Propagation Delay Time
Low−Side Driver
Output Resistance, Sourcing
Current
trDRVH, tfDRVH
tpdhDRVH
BST to SW = 0 V
BST to SW = 5 V, CLOAD = 1 nF
BST to SW = 5 V, CLOAD = 1 nF
10
kW
20
40
ns
25
45
70
ns
3.8
8
W
Output Resistance, Sinking
Current
1.5
8
W
Output Resistance, Unbiased
Transition Time
Propagation Delay Time (Note 3)
Timeout Delay (Note 4)
trDRVL, tfDRVL
tpdhDRVL
VCC = PGND
CLOAD = 1 nF
CLOAD = 1 nF
SW = 5 V
SW = PGND
10
20
15
150
300
150
300
kW
40
ns
35
ns
ns
Supply VCC
Supply Voltage Range
VCC
Supply Current
10
22
V
Normal Mode
Shutdown Mode
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
IVCC
IVCC(SD)
VUVLO
EN = 5 V
EN = 0 V
VCC rising
9.8
14
mA
1
10
mA
9
9.5
10
V
600
mV
DRV Regulator Output Voltage
VDRVREG
CL = 100 nF
5.0
5.25
5.5
V
DRV Regulator Output Current
IDRVREG
10
mA
1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
2. Measured between CSP and CSM. (VCSP − VCSM) = 96 mV x CSADJ/REFIN.
3. For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low.
4. The turn−on of DRVL is initiated after DRVH turns off by either SW crossing a ~1.0 V threshold or by examination of the timeout delay.
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