CY8C5466AXI-064 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY8C5466AXI-064 Datasheet PDF : 105 Pages
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PRELIMINARY
PSoC® 5: CY8C54 Family Datasheet
For more details on the peripherals see the “Example
Peripherals” section on page 32 of this data sheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem” section on page 32 of this data sheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 1% error over
temperature and voltage. The configurable analog subsystem
includes:
Analog muxes
Comparators
Analog mixers
Voltage references
ADCs
DACs
DFB
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals.
The CY8C54 family offers two successive approximation
register (SAR) ADCs. Featuring 12-bit conversions at up to 1 M
samples per second, they also offer low nonlinearity and offset
errors and SNR better than 70 dB. They are well suited for a
variety of higher speed analog applications.
The output of either ADC can optionally feed the programmable
DFB via DMA without CPU intervention. The designer can
configure the DFB to perform IIR and FIR digital filters and
several user defined custom functions. The DFB can implement
filters with up to 64 taps. It can perform a 48-bit
multiply-accumulate (MAC) operation in one clock cycle.
Four high speed voltage or current DACs support 8-bit output
signals at an update rate of up to 8 Msps. They can be routed
out of any GPIO pin. You can create higher resolution voltage
DAC outputs using the UDB array. This can be used to create a
pulse width modulated (PWM) DAC of up to 10 bits, at up to
48 kHz. The digital DACs in each UDB support PWM, PRS, or
delta-sigma algorithms with programmable widths.
In addition to the ADCs, DACs, and DFB, the analog subsystem
provides multiple:
Comparators
Uncommitted opamps
Configurable switched capacitor/continuous time (SC/CT)
blocks. These support:
Transimpedance amplifiers
Programmable gain amplifiers
Mixers
Other similar analog components
See the “Analog Subsystem” section on page 45 of this data
sheet for more details.
PSoC’s CPU subsystem is built around a 32-bit three-stage
pipelined ARM Cortex-M3 processor running at up to 67 MHz.
The Cortex-M3 includes a tightly integrated nested vectored
interrupt controller (NVIC) and various debug and trace modules.
The overall CPU subsystem includes a DMA controller, flash
cache, and RAM. The NVIC provides low latency, nested
interrupts, and tail-chaining of interrupts and other features to
increase the efficiency of interrupt handling. The DMA controller
enables peripherals to exchange data without CPU involvement.
This allows the CPU to run slower (saving power) or use those
CPU cycles to improve the performance of firmware algorithms.
The flash cache also reduces system power consumption by
allowing less frequent flash access.
PSoC’s nonvolatile subsystem consists of flash and
byte-writeable EEPROM. It provides up to 256 KB of on-chip
flash. The CPU can reprogram individual blocks of flash,
enabling boot loaders. A powerful and flexible protection model
secures the user's sensitive information, allowing selective
memory block locking for read and write protection. Two KB of
byte-writable EEPROM is available on-chip to store application
data.
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the VDDIO pins. Every GPIO
has analog I/O, LCD drive, flexible interrupt generation, slew rate
control, and digital I/O capability. The SIOs on PSoC allow VOH
to be set independently of VDDIO when used as outputs. When
SIOs are in input mode they are high impedance. This is true
even when the device is not powered or when the pin voltage
goes above the supply voltage. This makes the SIO ideally suited
for use on an I2C bus where the PSoC may not be powered when
other devices on the bus are. The SIO pins also have high
current sink capability for applications such as LED drives. The
programmable input threshold feature of the SIO can be used to
make the SIO function as a general purpose analog comparator.
For devices with FS USB the USB physical interface is also
provided (USBIO). When not using USB these pins may also be
used for limited digital functionality and device programming. All
the features of the PSoC I/Os are covered in detail in the “I/O
System and Routing” section on page 26 of this data sheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The Internal Main Oscillator (IMO) is the master clock base for
the system, and has 1% accuracy at 3 MHz. The IMO can be
configured to run from 3 MHz up to 62 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
system clock frequencies up to 67 MHz from the IMO, external
crystal, or external reference clock. It also contains a separate,
very low power Internal Low Speed Oscillator (ILO) for the sleep
and watchdog timers. A 32.768 KHz external watch crystal is
also supported for use in RTC applications. The clocks, together
with programmable clock dividers, provide the flexibility to
integrate most timing requirements.
The CY8C54 family supports a wide supply operating range from
1.71 to 5.5 V. This allows operation from regulated supplies such
as 1.8 ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%, or directly
from a wide range of battery types. In addition, it provides an
integrated high efficiency synchronous boost converter that can
power the device from supply voltages as low as 1,8 V. This
enables the device to be powered directly from a single battery
or solar cell. In addition, the designer can use the boost converter
to generate other voltages required by the device, such as a
3.3 V supply for LCD glass drive. The boost’s output is available
on the VBOOST pin, allowing other devices in the application to
be powered from the PSoC.
Document Number: 001-66238 Rev. **
Page 4 of 105
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